18c2ecf20Sopenharmony_ci* Amlogic Audio PDM input
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible: 'amlogic,axg-pdm' or
58c2ecf20Sopenharmony_ci	      'amlogic,g12a-pdm' or
68c2ecf20Sopenharmony_ci	      'amlogic,sm1-pdm'
78c2ecf20Sopenharmony_ci- reg: physical base address of the controller and length of memory
88c2ecf20Sopenharmony_ci       mapped region.
98c2ecf20Sopenharmony_ci- clocks: list of clock phandle, one for each entry clock-names.
108c2ecf20Sopenharmony_ci- clock-names: should contain the following:
118c2ecf20Sopenharmony_ci  * "pclk"   : peripheral clock.
128c2ecf20Sopenharmony_ci  * "dclk"   : pdm digital clock
138c2ecf20Sopenharmony_ci  * "sysclk" : dsp system clock
148c2ecf20Sopenharmony_ci- #sound-dai-cells: must be 0.
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ciOptional property:
178c2ecf20Sopenharmony_ci- resets: phandle to the dedicated reset line of the pdm input.
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ciExample of PDM on the A113 SoC:
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_cipdm: audio-controller@ff632000 {
228c2ecf20Sopenharmony_ci	compatible = "amlogic,axg-pdm";
238c2ecf20Sopenharmony_ci	reg = <0x0 0xff632000 0x0 0x34>;
248c2ecf20Sopenharmony_ci	#sound-dai-cells = <0>;
258c2ecf20Sopenharmony_ci	clocks = <&clkc_audio AUD_CLKID_PDM>,
268c2ecf20Sopenharmony_ci		 <&clkc_audio AUD_CLKID_PDM_DCLK>,
278c2ecf20Sopenharmony_ci		 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
288c2ecf20Sopenharmony_ci	clock-names = "pclk", "dclk", "sysclk";
298c2ecf20Sopenharmony_ci};
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