18c2ecf20Sopenharmony_ci* Amlogic Audio SPDIF Output
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible: 'amlogic,axg-spdifout' or
58c2ecf20Sopenharmony_ci	      'amlogic,g12a-spdifout' or
68c2ecf20Sopenharmony_ci	      'amlogic,sm1-spdifout'
78c2ecf20Sopenharmony_ci- clocks: list of clock phandle, one for each entry clock-names.
88c2ecf20Sopenharmony_ci- clock-names: should contain the following:
98c2ecf20Sopenharmony_ci  * "pclk" : peripheral clock.
108c2ecf20Sopenharmony_ci  * "mclk" : master clock
118c2ecf20Sopenharmony_ci- #sound-dai-cells: must be 0.
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ciOptional property:
148c2ecf20Sopenharmony_ci- resets: phandle to the dedicated reset line of the spdif output.
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ciExample on the A113 SoC:
178c2ecf20Sopenharmony_ci
188c2ecf20Sopenharmony_cispdifout: audio-controller@480 {
198c2ecf20Sopenharmony_ci	compatible = "amlogic,axg-spdifout";
208c2ecf20Sopenharmony_ci	reg = <0x0 0x480 0x0 0x50>;
218c2ecf20Sopenharmony_ci	#sound-dai-cells = <0>;
228c2ecf20Sopenharmony_ci	clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
238c2ecf20Sopenharmony_ci		 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
248c2ecf20Sopenharmony_ci	clock-names = "pclk", "mclk";
258c2ecf20Sopenharmony_ci};
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