18c2ecf20Sopenharmony_ci* VIA VT8500 and WonderMedia WM8xxx UART Controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
58c2ecf20Sopenharmony_ci	including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ci- reg: base physical address of the controller and length of memory mapped
88c2ecf20Sopenharmony_ci	region.
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ci- interrupts: hardware interrupt number
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128c2ecf20Sopenharmony_ci- clocks: shall be the input parent clock phandle for the clock. This should
138c2ecf20Sopenharmony_ci	be the 24Mhz reference clock.
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ciAliases may be defined to ensure the correct ordering of the uarts.
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178c2ecf20Sopenharmony_ciExample:
188c2ecf20Sopenharmony_ci	aliases {
198c2ecf20Sopenharmony_ci		serial0 = &uart0;
208c2ecf20Sopenharmony_ci	};
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ci	uart0: serial@d8200000 {
238c2ecf20Sopenharmony_ci		compatible = "via,vt8500-uart";
248c2ecf20Sopenharmony_ci		reg = <0xd8200000 0x1040>;
258c2ecf20Sopenharmony_ci		interrupts = <32>;
268c2ecf20Sopenharmony_ci		clocks = <&clkuart0>;
278c2ecf20Sopenharmony_ci	};
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