18c2ecf20Sopenharmony_ci* CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter * 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci- compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart", 58c2ecf20Sopenharmony_ci "sirf,atlas7-uart" or "sirf,atlas7-usp-uart". 68c2ecf20Sopenharmony_ci- reg : Offset and length of the register set for the device 78c2ecf20Sopenharmony_ci- interrupts : Should contain uart interrupt 88c2ecf20Sopenharmony_ci- fifosize : Should define hardware rx/tx fifo size 98c2ecf20Sopenharmony_ci- clocks : Should contain uart clock number 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ciOptional properties: 128c2ecf20Sopenharmony_ci- uart-has-rtscts: we have hardware flow controller pins in hardware 138c2ecf20Sopenharmony_ci- rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true 148c2ecf20Sopenharmony_ci- cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciExample: 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciuart0: uart@b0050000 { 198c2ecf20Sopenharmony_ci cell-index = <0>; 208c2ecf20Sopenharmony_ci compatible = "sirf,prima2-uart"; 218c2ecf20Sopenharmony_ci reg = <0xb0050000 0x1000>; 228c2ecf20Sopenharmony_ci interrupts = <17>; 238c2ecf20Sopenharmony_ci fifosize = <128>; 248c2ecf20Sopenharmony_ci clocks = <&clks 13>; 258c2ecf20Sopenharmony_ci}; 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ciOn the board-specific dts, we can put rts-gpios and cts-gpios like 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ciusp@b0090000 { 308c2ecf20Sopenharmony_ci compatible = "sirf,prima2-usp-uart"; 318c2ecf20Sopenharmony_ci uart-has-rtscts; 328c2ecf20Sopenharmony_ci rts-gpios = <&gpio 15 0>; 338c2ecf20Sopenharmony_ci cts-gpios = <&gpio 46 0>; 348c2ecf20Sopenharmony_ci}; 35