18c2ecf20Sopenharmony_ci* MSM Serial UART 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe MSM serial UART hardware is designed for low-speed use cases where a 48c2ecf20Sopenharmony_cidma-engine isn't needed. From a software perspective it's mostly compatible 58c2ecf20Sopenharmony_ciwith the MSM serial UARTDM except that it only supports reading and writing one 68c2ecf20Sopenharmony_cicharacter at a time. 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciRequired properties: 98c2ecf20Sopenharmony_ci- compatible: Should contain "qcom,msm-uart" 108c2ecf20Sopenharmony_ci- reg: Should contain UART register location and length. 118c2ecf20Sopenharmony_ci- interrupts: Should contain UART interrupt. 128c2ecf20Sopenharmony_ci- clocks: Should contain the core clock. 138c2ecf20Sopenharmony_ci- clock-names: Should be "core". 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciExample: 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciA uart device at 0xa9c00000 with interrupt 11. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciserial@a9c00000 { 208c2ecf20Sopenharmony_ci compatible = "qcom,msm-uart"; 218c2ecf20Sopenharmony_ci reg = <0xa9c00000 0x1000>; 228c2ecf20Sopenharmony_ci interrupts = <11>; 238c2ecf20Sopenharmony_ci clocks = <&uart_cxc>; 248c2ecf20Sopenharmony_ci clock-names = "core"; 258c2ecf20Sopenharmony_ci}; 26