18c2ecf20Sopenharmony_ciAtmel AT91SAM9260 Real Time Timer 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci- compatible: should be one of the following: 58c2ecf20Sopenharmony_ci - "atmel,at91sam9260-rtt" 68c2ecf20Sopenharmony_ci - "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt" 78c2ecf20Sopenharmony_ci- reg: should encode the memory region of the RTT controller 88c2ecf20Sopenharmony_ci- interrupts: rtt alarm/event interrupt 98c2ecf20Sopenharmony_ci- clocks: should contain the 32 KHz slow clk that will drive the RTT block. 108c2ecf20Sopenharmony_ci- atmel,rtt-rtc-time-reg: should encode the GPBR register used to store 118c2ecf20Sopenharmony_ci the time base when the RTT is used as an RTC. 128c2ecf20Sopenharmony_ci The first cell should point to the GPBR node and the second one 138c2ecf20Sopenharmony_ci encode the offset within the GPBR block (or in other words, the 148c2ecf20Sopenharmony_ci GPBR register used to store the time base). 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciExample: 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_cirtt@fffffd20 { 208c2ecf20Sopenharmony_ci compatible = "atmel,at91sam9260-rtt"; 218c2ecf20Sopenharmony_ci reg = <0xfffffd20 0x10>; 228c2ecf20Sopenharmony_ci interrupts = <1 4 7>; 238c2ecf20Sopenharmony_ci clocks = <&clk32k>; 248c2ecf20Sopenharmony_ci atmel,rtt-rtc-time-reg = <&gpbr 0x0>; 258c2ecf20Sopenharmony_ci}; 26