18c2ecf20Sopenharmony_ciXilinx Zynq Reset Manager 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe Zynq AP-SoC has several different resets. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciSee Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci- compatible: "xlnx,zynq-reset" 98c2ecf20Sopenharmony_ci- reg: SLCR offset and size taken via syscon <0x200 0x48> 108c2ecf20Sopenharmony_ci- syscon: <&slcr> 118c2ecf20Sopenharmony_ci This should be a phandle to the Zynq's SLCR registers. 128c2ecf20Sopenharmony_ci- #reset-cells: Must be 1 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ciThe Zynq Reset Manager needs to be a childnode of the SLCR. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciExample: 178c2ecf20Sopenharmony_ci rstc: rstc@200 { 188c2ecf20Sopenharmony_ci compatible = "xlnx,zynq-reset"; 198c2ecf20Sopenharmony_ci reg = <0x200 0x48>; 208c2ecf20Sopenharmony_ci #reset-cells = <1>; 218c2ecf20Sopenharmony_ci syscon = <&slcr>; 228c2ecf20Sopenharmony_ci }; 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ciReset outputs: 258c2ecf20Sopenharmony_ci 0 : soft reset 268c2ecf20Sopenharmony_ci 32 : ddr reset 278c2ecf20Sopenharmony_ci 64 : topsw reset 288c2ecf20Sopenharmony_ci 96 : dmac reset 298c2ecf20Sopenharmony_ci 128: usb0 reset 308c2ecf20Sopenharmony_ci 129: usb1 reset 318c2ecf20Sopenharmony_ci 160: gem0 reset 328c2ecf20Sopenharmony_ci 161: gem1 reset 338c2ecf20Sopenharmony_ci 164: gem0 rx reset 348c2ecf20Sopenharmony_ci 165: gem1 rx reset 358c2ecf20Sopenharmony_ci 166: gem0 ref reset 368c2ecf20Sopenharmony_ci 167: gem1 ref reset 378c2ecf20Sopenharmony_ci 192: sdio0 reset 388c2ecf20Sopenharmony_ci 193: sdio1 reset 398c2ecf20Sopenharmony_ci 196: sdio0 ref reset 408c2ecf20Sopenharmony_ci 197: sdio1 ref reset 418c2ecf20Sopenharmony_ci 224: spi0 reset 428c2ecf20Sopenharmony_ci 225: spi1 reset 438c2ecf20Sopenharmony_ci 226: spi0 ref reset 448c2ecf20Sopenharmony_ci 227: spi1 ref reset 458c2ecf20Sopenharmony_ci 256: can0 reset 468c2ecf20Sopenharmony_ci 257: can1 reset 478c2ecf20Sopenharmony_ci 258: can0 ref reset 488c2ecf20Sopenharmony_ci 259: can1 ref reset 498c2ecf20Sopenharmony_ci 288: i2c0 reset 508c2ecf20Sopenharmony_ci 289: i2c1 reset 518c2ecf20Sopenharmony_ci 320: uart0 reset 528c2ecf20Sopenharmony_ci 321: uart1 reset 538c2ecf20Sopenharmony_ci 322: uart0 ref reset 548c2ecf20Sopenharmony_ci 323: uart1 ref reset 558c2ecf20Sopenharmony_ci 352: gpio reset 568c2ecf20Sopenharmony_ci 384: lqspi reset 578c2ecf20Sopenharmony_ci 385: qspi ref reset 588c2ecf20Sopenharmony_ci 416: smc reset 598c2ecf20Sopenharmony_ci 417: smc ref reset 608c2ecf20Sopenharmony_ci 448: ocm reset 618c2ecf20Sopenharmony_ci 512: fpga0 out reset 628c2ecf20Sopenharmony_ci 513: fpga1 out reset 638c2ecf20Sopenharmony_ci 514: fpga2 out reset 648c2ecf20Sopenharmony_ci 515: fpga3 out reset 658c2ecf20Sopenharmony_ci 544: a9 reset 0 668c2ecf20Sopenharmony_ci 545: a9 reset 1 678c2ecf20Sopenharmony_ci 552: peri reset 688c2ecf20Sopenharmony_ci 69