18c2ecf20Sopenharmony_ciBinding for the AXS10x reset controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis binding describes the ARC AXS10x boards custom IP-block which allows 48c2ecf20Sopenharmony_cito control reset signals of selected peripherals. For example DW GMAC, etc... 58c2ecf20Sopenharmony_ciThis block is controlled via memory-mapped register (AKA CREG) which 68c2ecf20Sopenharmony_cirepresents up-to 32 reset lines. 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciAs of today only the following lines are used: 98c2ecf20Sopenharmony_ci - DW GMAC - line 5 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ciThis binding uses the common reset binding[1]. 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/reset/reset.txt 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciRequired properties: 168c2ecf20Sopenharmony_ci- compatible: should be "snps,axs10x-reset". 178c2ecf20Sopenharmony_ci- reg: should always contain pair address - length: for creg reset 188c2ecf20Sopenharmony_ci bits register. 198c2ecf20Sopenharmony_ci- #reset-cells: from common reset binding; Should always be set to 1. 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ciExample: 228c2ecf20Sopenharmony_ci reset: reset-controller@11220 { 238c2ecf20Sopenharmony_ci compatible = "snps,axs10x-reset"; 248c2ecf20Sopenharmony_ci #reset-cells = <1>; 258c2ecf20Sopenharmony_ci reg = <0x11220 0x4>; 268c2ecf20Sopenharmony_ci }; 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ciSpecifying reset lines connected to IP modules: 298c2ecf20Sopenharmony_ci ethernet@.... { 308c2ecf20Sopenharmony_ci .... 318c2ecf20Sopenharmony_ci resets = <&reset 5>; 328c2ecf20Sopenharmony_ci .... 338c2ecf20Sopenharmony_ci }; 34