18c2ecf20Sopenharmony_ciNXP LPC1850 Reset Generation Unit (RGU) 28c2ecf20Sopenharmony_ci======================================== 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciPlease also refer to reset.txt in this directory for common reset 58c2ecf20Sopenharmony_cicontroller binding usage. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci- compatible: Should be "nxp,lpc1850-rgu" 98c2ecf20Sopenharmony_ci- reg: register base and length 108c2ecf20Sopenharmony_ci- clocks: phandle and clock specifier to RGU clocks 118c2ecf20Sopenharmony_ci- clock-names: should contain "delay" and "reg" 128c2ecf20Sopenharmony_ci- #reset-cells: should be 1 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ciSee table below for valid peripheral reset numbers. Numbers not 158c2ecf20Sopenharmony_ciin the table below are either reserved or not applicable for 168c2ecf20Sopenharmony_cinormal operation. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciReset Peripheral 198c2ecf20Sopenharmony_ci 9 System control unit (SCU) 208c2ecf20Sopenharmony_ci 12 ARM Cortex-M0 subsystem core (LPC43xx only) 218c2ecf20Sopenharmony_ci 13 CPU core 228c2ecf20Sopenharmony_ci 16 LCD controller 238c2ecf20Sopenharmony_ci 17 USB0 248c2ecf20Sopenharmony_ci 18 USB1 258c2ecf20Sopenharmony_ci 19 DMA 268c2ecf20Sopenharmony_ci 20 SDIO 278c2ecf20Sopenharmony_ci 21 External memory controller (EMC) 288c2ecf20Sopenharmony_ci 22 Ethernet 298c2ecf20Sopenharmony_ci 25 Flash bank A 308c2ecf20Sopenharmony_ci 27 EEPROM 318c2ecf20Sopenharmony_ci 28 GPIO 328c2ecf20Sopenharmony_ci 29 Flash bank B 338c2ecf20Sopenharmony_ci 32 Timer0 348c2ecf20Sopenharmony_ci 33 Timer1 358c2ecf20Sopenharmony_ci 34 Timer2 368c2ecf20Sopenharmony_ci 35 Timer3 378c2ecf20Sopenharmony_ci 36 Repetitive Interrupt timer (RIT) 388c2ecf20Sopenharmony_ci 37 State Configurable Timer (SCT) 398c2ecf20Sopenharmony_ci 38 Motor control PWM (MCPWM) 408c2ecf20Sopenharmony_ci 39 QEI 418c2ecf20Sopenharmony_ci 40 ADC0 428c2ecf20Sopenharmony_ci 41 ADC1 438c2ecf20Sopenharmony_ci 42 DAC 448c2ecf20Sopenharmony_ci 44 USART0 458c2ecf20Sopenharmony_ci 45 UART1 468c2ecf20Sopenharmony_ci 46 USART2 478c2ecf20Sopenharmony_ci 47 USART3 488c2ecf20Sopenharmony_ci 48 I2C0 498c2ecf20Sopenharmony_ci 49 I2C1 508c2ecf20Sopenharmony_ci 50 SSP0 518c2ecf20Sopenharmony_ci 51 SSP1 528c2ecf20Sopenharmony_ci 52 I2S0 and I2S1 538c2ecf20Sopenharmony_ci 53 Serial Flash Interface (SPIFI) 548c2ecf20Sopenharmony_ci 54 C_CAN1 558c2ecf20Sopenharmony_ci 55 C_CAN0 568c2ecf20Sopenharmony_ci 56 ARM Cortex-M0 application core (LPC4370 only) 578c2ecf20Sopenharmony_ci 57 SGPIO (LPC43xx only) 588c2ecf20Sopenharmony_ci 58 SPI (LPC43xx only) 598c2ecf20Sopenharmony_ci 60 ADCHS (12-bit ADC) (LPC4370 only) 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ciRefer to NXP LPC18xx or LPC43xx user manual for more details about 628c2ecf20Sopenharmony_cithe reset signals and the connected block/peripheral. 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_ciReset provider example: 658c2ecf20Sopenharmony_cirgu: reset-controller@40053000 { 668c2ecf20Sopenharmony_ci compatible = "nxp,lpc1850-rgu"; 678c2ecf20Sopenharmony_ci reg = <0x40053000 0x1000>; 688c2ecf20Sopenharmony_ci clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; 698c2ecf20Sopenharmony_ci clock-names = "delay", "reg"; 708c2ecf20Sopenharmony_ci #reset-cells = <1>; 718c2ecf20Sopenharmony_ci}; 728c2ecf20Sopenharmony_ci 738c2ecf20Sopenharmony_ciReset consumer example: 748c2ecf20Sopenharmony_cimac: ethernet@40010000 { 758c2ecf20Sopenharmony_ci compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; 768c2ecf20Sopenharmony_ci reg = <0x40010000 0x2000>; 778c2ecf20Sopenharmony_ci interrupts = <5>; 788c2ecf20Sopenharmony_ci interrupt-names = "macirq"; 798c2ecf20Sopenharmony_ci clocks = <&ccu1 CLK_CPU_ETHERNET>; 808c2ecf20Sopenharmony_ci clock-names = "stmmaceth"; 818c2ecf20Sopenharmony_ci resets = <&rgu 22>; 828c2ecf20Sopenharmony_ci reset-names = "stmmaceth"; 838c2ecf20Sopenharmony_ci}; 84