18c2ecf20Sopenharmony_ciHisilicon System Reset Controller 28c2ecf20Sopenharmony_ci====================================== 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciPlease also refer to reset.txt in this directory for common reset 58c2ecf20Sopenharmony_cicontroller binding usage. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciThe reset controller registers are part of the system-ctl block on 88c2ecf20Sopenharmony_cihi6220 SoC. 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ciRequired properties: 118c2ecf20Sopenharmony_ci- compatible: should be one of the following: 128c2ecf20Sopenharmony_ci - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller. 138c2ecf20Sopenharmony_ci - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller. 148c2ecf20Sopenharmony_ci - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller. 158c2ecf20Sopenharmony_ci- reg: should be register base and length as documented in the 168c2ecf20Sopenharmony_ci datasheet 178c2ecf20Sopenharmony_ci- #reset-cells: 1, see below 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciExample: 208c2ecf20Sopenharmony_cisys_ctrl: sys_ctrl@f7030000 { 218c2ecf20Sopenharmony_ci compatible = "hisilicon,hi6220-sysctrl", "syscon"; 228c2ecf20Sopenharmony_ci reg = <0x0 0xf7030000 0x0 0x2000>; 238c2ecf20Sopenharmony_ci #clock-cells = <1>; 248c2ecf20Sopenharmony_ci #reset-cells = <1>; 258c2ecf20Sopenharmony_ci}; 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ciSpecifying reset lines connected to IP modules 288c2ecf20Sopenharmony_ci============================================== 298c2ecf20Sopenharmony_ciexample: 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci uart1: serial@..... { 328c2ecf20Sopenharmony_ci ... 338c2ecf20Sopenharmony_ci resets = <&sys_ctrl PERIPH_RSTEN3_UART1>; 348c2ecf20Sopenharmony_ci ... 358c2ecf20Sopenharmony_ci }; 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ciThe index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>. 38