18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 28c2ecf20Sopenharmony_ci%YAML 1.2 38c2ecf20Sopenharmony_ci--- 48c2ecf20Sopenharmony_ci$id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml# 58c2ecf20Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_cititle: TI K3 DSP devices 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_cimaintainers: 108c2ecf20Sopenharmony_ci - Suman Anna <s-anna@ti.com> 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_cidescription: | 138c2ecf20Sopenharmony_ci The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems 148c2ecf20Sopenharmony_ci that are used to offload some of the processor-intensive tasks or algorithms, 158c2ecf20Sopenharmony_ci for achieving various system level goals. 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci These processor sub-systems usually contain additional sub-modules like 188c2ecf20Sopenharmony_ci L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory 198c2ecf20Sopenharmony_ci controller, a dedicated local power/sleep controller etc. The DSP processor 208c2ecf20Sopenharmony_ci cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a 218c2ecf20Sopenharmony_ci TMS320C71x CorePac processor. 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci Each DSP Core sub-system is represented as a single DT node. Each node has a 248c2ecf20Sopenharmony_ci number of required or optional properties that enable the OS running on the 258c2ecf20Sopenharmony_ci host processor (Arm CorePac) to perform the device management of the remote 268c2ecf20Sopenharmony_ci processor and to communicate with the remote processor. 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ciallOf: 298c2ecf20Sopenharmony_ci - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ciproperties: 328c2ecf20Sopenharmony_ci compatible: 338c2ecf20Sopenharmony_ci enum: 348c2ecf20Sopenharmony_ci - ti,j721e-c66-dsp 358c2ecf20Sopenharmony_ci - ti,j721e-c71-dsp 368c2ecf20Sopenharmony_ci description: 378c2ecf20Sopenharmony_ci Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs 388c2ecf20Sopenharmony_ci Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ci resets: 418c2ecf20Sopenharmony_ci description: | 428c2ecf20Sopenharmony_ci Should contain the phandle to the reset controller node managing the 438c2ecf20Sopenharmony_ci local resets for this device, and a reset specifier. 448c2ecf20Sopenharmony_ci maxItems: 1 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci firmware-name: 478c2ecf20Sopenharmony_ci description: | 488c2ecf20Sopenharmony_ci Should contain the name of the default firmware image 498c2ecf20Sopenharmony_ci file located on the firmware search path 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci mboxes: 528c2ecf20Sopenharmony_ci description: | 538c2ecf20Sopenharmony_ci OMAP Mailbox specifier denoting the sub-mailbox, to be used for 548c2ecf20Sopenharmony_ci communication with the remote processor. This property should match 558c2ecf20Sopenharmony_ci with the sub-mailbox node used in the firmware image. 568c2ecf20Sopenharmony_ci maxItems: 1 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci memory-region: 598c2ecf20Sopenharmony_ci minItems: 2 608c2ecf20Sopenharmony_ci maxItems: 8 618c2ecf20Sopenharmony_ci description: | 628c2ecf20Sopenharmony_ci phandle to the reserved memory nodes to be associated with the remoteproc 638c2ecf20Sopenharmony_ci device. There should be at least two reserved memory nodes defined. The 648c2ecf20Sopenharmony_ci reserved memory nodes should be carveout nodes, and should be defined as 658c2ecf20Sopenharmony_ci per the bindings in 668c2ecf20Sopenharmony_ci Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt 678c2ecf20Sopenharmony_ci items: 688c2ecf20Sopenharmony_ci - description: region used for dynamic DMA allocations like vrings and 698c2ecf20Sopenharmony_ci vring buffers 708c2ecf20Sopenharmony_ci - description: region reserved for firmware image sections 718c2ecf20Sopenharmony_ci additionalItems: true 728c2ecf20Sopenharmony_ci 738c2ecf20Sopenharmony_ci# Optional properties: 748c2ecf20Sopenharmony_ci# -------------------- 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci sram: 778c2ecf20Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/phandle-array 788c2ecf20Sopenharmony_ci minItems: 1 798c2ecf20Sopenharmony_ci maxItems: 4 808c2ecf20Sopenharmony_ci description: | 818c2ecf20Sopenharmony_ci phandles to one or more reserved on-chip SRAM regions. The regions 828c2ecf20Sopenharmony_ci should be defined as child nodes of the respective SRAM node, and 838c2ecf20Sopenharmony_ci should be defined as per the generic bindings in, 848c2ecf20Sopenharmony_ci Documentation/devicetree/bindings/sram/sram.yaml 858c2ecf20Sopenharmony_ci 868c2ecf20Sopenharmony_ciif: 878c2ecf20Sopenharmony_ci properties: 888c2ecf20Sopenharmony_ci compatible: 898c2ecf20Sopenharmony_ci enum: 908c2ecf20Sopenharmony_ci - ti,j721e-c66-dsp 918c2ecf20Sopenharmony_cithen: 928c2ecf20Sopenharmony_ci properties: 938c2ecf20Sopenharmony_ci reg: 948c2ecf20Sopenharmony_ci items: 958c2ecf20Sopenharmony_ci - description: Address and Size of the L2 SRAM internal memory region 968c2ecf20Sopenharmony_ci - description: Address and Size of the L1 PRAM internal memory region 978c2ecf20Sopenharmony_ci - description: Address and Size of the L1 DRAM internal memory region 988c2ecf20Sopenharmony_ci reg-names: 998c2ecf20Sopenharmony_ci items: 1008c2ecf20Sopenharmony_ci - const: l2sram 1018c2ecf20Sopenharmony_ci - const: l1pram 1028c2ecf20Sopenharmony_ci - const: l1dram 1038c2ecf20Sopenharmony_cielse: 1048c2ecf20Sopenharmony_ci if: 1058c2ecf20Sopenharmony_ci properties: 1068c2ecf20Sopenharmony_ci compatible: 1078c2ecf20Sopenharmony_ci enum: 1088c2ecf20Sopenharmony_ci - ti,j721e-c71-dsp 1098c2ecf20Sopenharmony_ci then: 1108c2ecf20Sopenharmony_ci properties: 1118c2ecf20Sopenharmony_ci reg: 1128c2ecf20Sopenharmony_ci items: 1138c2ecf20Sopenharmony_ci - description: Address and Size of the L2 SRAM internal memory region 1148c2ecf20Sopenharmony_ci - description: Address and Size of the L1 DRAM internal memory region 1158c2ecf20Sopenharmony_ci reg-names: 1168c2ecf20Sopenharmony_ci items: 1178c2ecf20Sopenharmony_ci - const: l2sram 1188c2ecf20Sopenharmony_ci - const: l1dram 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_cirequired: 1218c2ecf20Sopenharmony_ci - compatible 1228c2ecf20Sopenharmony_ci - reg 1238c2ecf20Sopenharmony_ci - reg-names 1248c2ecf20Sopenharmony_ci - ti,sci 1258c2ecf20Sopenharmony_ci - ti,sci-dev-id 1268c2ecf20Sopenharmony_ci - ti,sci-proc-ids 1278c2ecf20Sopenharmony_ci - resets 1288c2ecf20Sopenharmony_ci - firmware-name 1298c2ecf20Sopenharmony_ci - mboxes 1308c2ecf20Sopenharmony_ci - memory-region 1318c2ecf20Sopenharmony_ci 1328c2ecf20Sopenharmony_ciunevaluatedProperties: false 1338c2ecf20Sopenharmony_ci 1348c2ecf20Sopenharmony_ciexamples: 1358c2ecf20Sopenharmony_ci - | 1368c2ecf20Sopenharmony_ci / { 1378c2ecf20Sopenharmony_ci model = "Texas Instruments K3 J721E SoC"; 1388c2ecf20Sopenharmony_ci compatible = "ti,j721e"; 1398c2ecf20Sopenharmony_ci #address-cells = <2>; 1408c2ecf20Sopenharmony_ci #size-cells = <2>; 1418c2ecf20Sopenharmony_ci 1428c2ecf20Sopenharmony_ci bus@100000 { 1438c2ecf20Sopenharmony_ci compatible = "simple-bus"; 1448c2ecf20Sopenharmony_ci #address-cells = <2>; 1458c2ecf20Sopenharmony_ci #size-cells = <2>; 1468c2ecf20Sopenharmony_ci ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 1478c2ecf20Sopenharmony_ci <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */ 1488c2ecf20Sopenharmony_ci <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ 1498c2ecf20Sopenharmony_ci <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */ 1508c2ecf20Sopenharmony_ci 1518c2ecf20Sopenharmony_ci /* J721E C66_0 DSP node */ 1528c2ecf20Sopenharmony_ci dsp@4d80800000 { 1538c2ecf20Sopenharmony_ci compatible = "ti,j721e-c66-dsp"; 1548c2ecf20Sopenharmony_ci reg = <0x4d 0x80800000 0x00 0x00048000>, 1558c2ecf20Sopenharmony_ci <0x4d 0x80e00000 0x00 0x00008000>, 1568c2ecf20Sopenharmony_ci <0x4d 0x80f00000 0x00 0x00008000>; 1578c2ecf20Sopenharmony_ci reg-names = "l2sram", "l1pram", "l1dram"; 1588c2ecf20Sopenharmony_ci ti,sci = <&dmsc>; 1598c2ecf20Sopenharmony_ci ti,sci-dev-id = <142>; 1608c2ecf20Sopenharmony_ci ti,sci-proc-ids = <0x03 0xFF>; 1618c2ecf20Sopenharmony_ci resets = <&k3_reset 142 1>; 1628c2ecf20Sopenharmony_ci firmware-name = "j7-c66_0-fw"; 1638c2ecf20Sopenharmony_ci memory-region = <&c66_0_dma_memory_region>, 1648c2ecf20Sopenharmony_ci <&c66_0_memory_region>; 1658c2ecf20Sopenharmony_ci mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 1668c2ecf20Sopenharmony_ci }; 1678c2ecf20Sopenharmony_ci 1688c2ecf20Sopenharmony_ci /* J721E C71_0 DSP node */ 1698c2ecf20Sopenharmony_ci c71_0: dsp@64800000 { 1708c2ecf20Sopenharmony_ci compatible = "ti,j721e-c71-dsp"; 1718c2ecf20Sopenharmony_ci reg = <0x00 0x64800000 0x00 0x00080000>, 1728c2ecf20Sopenharmony_ci <0x00 0x64e00000 0x00 0x0000c000>; 1738c2ecf20Sopenharmony_ci reg-names = "l2sram", "l1dram"; 1748c2ecf20Sopenharmony_ci ti,sci = <&dmsc>; 1758c2ecf20Sopenharmony_ci ti,sci-dev-id = <15>; 1768c2ecf20Sopenharmony_ci ti,sci-proc-ids = <0x30 0xFF>; 1778c2ecf20Sopenharmony_ci resets = <&k3_reset 15 1>; 1788c2ecf20Sopenharmony_ci firmware-name = "j7-c71_0-fw"; 1798c2ecf20Sopenharmony_ci memory-region = <&c71_0_dma_memory_region>, 1808c2ecf20Sopenharmony_ci <&c71_0_memory_region>; 1818c2ecf20Sopenharmony_ci mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1828c2ecf20Sopenharmony_ci }; 1838c2ecf20Sopenharmony_ci }; 1848c2ecf20Sopenharmony_ci }; 185