18c2ecf20Sopenharmony_ciQualcomm Technology Inc. Hexagon v56 Peripheral Image Loader 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis document defines the binding for a component that loads and boots firmware 48c2ecf20Sopenharmony_cion the Qualcomm Technology Inc. Hexagon v56 core. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci- compatible: 78c2ecf20Sopenharmony_ci Usage: required 88c2ecf20Sopenharmony_ci Value type: <string> 98c2ecf20Sopenharmony_ci Definition: must be one of: 108c2ecf20Sopenharmony_ci "qcom,qcs404-cdsp-pil", 118c2ecf20Sopenharmony_ci "qcom,sdm845-adsp-pil" 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci- reg: 148c2ecf20Sopenharmony_ci Usage: required 158c2ecf20Sopenharmony_ci Value type: <prop-encoded-array> 168c2ecf20Sopenharmony_ci Definition: must specify the base address and size of the qdsp6ss register 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci- interrupts-extended: 198c2ecf20Sopenharmony_ci Usage: required 208c2ecf20Sopenharmony_ci Value type: <prop-encoded-array> 218c2ecf20Sopenharmony_ci Definition: must list the watchdog, fatal IRQs ready, handover and 228c2ecf20Sopenharmony_ci stop-ack IRQs 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci- interrupt-names: 258c2ecf20Sopenharmony_ci Usage: required 268c2ecf20Sopenharmony_ci Value type: <stringlist> 278c2ecf20Sopenharmony_ci Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci- clocks: 308c2ecf20Sopenharmony_ci Usage: required 318c2ecf20Sopenharmony_ci Value type: <prop-encoded-array> 328c2ecf20Sopenharmony_ci Definition: List of phandles and clock specifier pairs for the Hexagon, 338c2ecf20Sopenharmony_ci per clock-names below. 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci- clock-names: 368c2ecf20Sopenharmony_ci Usage: required for SDM845 ADSP 378c2ecf20Sopenharmony_ci Value type: <stringlist> 388c2ecf20Sopenharmony_ci Definition: List of clock input name strings sorted in the same 398c2ecf20Sopenharmony_ci order as the clocks property. Definition must have 408c2ecf20Sopenharmony_ci "xo", "sway_cbcr", "lpass_ahbs_aon_cbcr", 418c2ecf20Sopenharmony_ci "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep" 428c2ecf20Sopenharmony_ci and "qdsp6ss_core". 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci- clock-names: 458c2ecf20Sopenharmony_ci Usage: required for QCS404 CDSP 468c2ecf20Sopenharmony_ci Value type: <stringlist> 478c2ecf20Sopenharmony_ci Definition: List of clock input name strings sorted in the same 488c2ecf20Sopenharmony_ci order as the clocks property. Definition must have 498c2ecf20Sopenharmony_ci "xo", "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", 508c2ecf20Sopenharmony_ci "q6ss_master", "q6_axim". 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci- power-domains: 538c2ecf20Sopenharmony_ci Usage: required 548c2ecf20Sopenharmony_ci Value type: <phandle> 558c2ecf20Sopenharmony_ci Definition: reference to cx power domain node. 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci- resets: 588c2ecf20Sopenharmony_ci Usage: required 598c2ecf20Sopenharmony_ci Value type: <phandle> 608c2ecf20Sopenharmony_ci Definition: reference to the list of resets for the Hexagon. 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_ci- reset-names: 638c2ecf20Sopenharmony_ci Usage: required for SDM845 ADSP 648c2ecf20Sopenharmony_ci Value type: <stringlist> 658c2ecf20Sopenharmony_ci Definition: must be "pdc_sync" and "cc_lpass" 668c2ecf20Sopenharmony_ci 678c2ecf20Sopenharmony_ci- reset-names: 688c2ecf20Sopenharmony_ci Usage: required for QCS404 CDSP 698c2ecf20Sopenharmony_ci Value type: <stringlist> 708c2ecf20Sopenharmony_ci Definition: must be "restart" 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci- qcom,halt-regs: 738c2ecf20Sopenharmony_ci Usage: required 748c2ecf20Sopenharmony_ci Value type: <prop-encoded-array> 758c2ecf20Sopenharmony_ci Definition: a phandle reference to a syscon representing TCSR followed 768c2ecf20Sopenharmony_ci by the offset within syscon for Hexagon halt register. 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ci- memory-region: 798c2ecf20Sopenharmony_ci Usage: required 808c2ecf20Sopenharmony_ci Value type: <phandle> 818c2ecf20Sopenharmony_ci Definition: reference to the reserved-memory for the firmware 828c2ecf20Sopenharmony_ci 838c2ecf20Sopenharmony_ci- qcom,smem-states: 848c2ecf20Sopenharmony_ci Usage: required 858c2ecf20Sopenharmony_ci Value type: <phandle> 868c2ecf20Sopenharmony_ci Definition: reference to the smem state for requesting the Hexagon to 878c2ecf20Sopenharmony_ci shut down 888c2ecf20Sopenharmony_ci 898c2ecf20Sopenharmony_ci- qcom,smem-state-names: 908c2ecf20Sopenharmony_ci Usage: required 918c2ecf20Sopenharmony_ci Value type: <stringlist> 928c2ecf20Sopenharmony_ci Definition: must be "stop" 938c2ecf20Sopenharmony_ci 948c2ecf20Sopenharmony_ci 958c2ecf20Sopenharmony_ci= SUBNODES 968c2ecf20Sopenharmony_ciThe adsp node may have an subnode named "glink-edge" that describes the 978c2ecf20Sopenharmony_cicommunication edge, channels and devices related to the Hexagon. 988c2ecf20Sopenharmony_ciSee ../soc/qcom/qcom,glink.txt for details on how to describe these. 998c2ecf20Sopenharmony_ci 1008c2ecf20Sopenharmony_ci= EXAMPLE 1018c2ecf20Sopenharmony_ciThe following example describes the resources needed to boot control the 1028c2ecf20Sopenharmony_ciADSP, as it is found on SDM845 boards. 1038c2ecf20Sopenharmony_ci 1048c2ecf20Sopenharmony_ci remoteproc@17300000 { 1058c2ecf20Sopenharmony_ci compatible = "qcom,sdm845-adsp-pil"; 1068c2ecf20Sopenharmony_ci reg = <0x17300000 0x40c>; 1078c2ecf20Sopenharmony_ci 1088c2ecf20Sopenharmony_ci interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 1098c2ecf20Sopenharmony_ci <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1108c2ecf20Sopenharmony_ci <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1118c2ecf20Sopenharmony_ci <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1128c2ecf20Sopenharmony_ci <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1138c2ecf20Sopenharmony_ci interrupt-names = "wdog", "fatal", "ready", 1148c2ecf20Sopenharmony_ci "handover", "stop-ack"; 1158c2ecf20Sopenharmony_ci 1168c2ecf20Sopenharmony_ci clocks = <&rpmhcc RPMH_CXO_CLK>, 1178c2ecf20Sopenharmony_ci <&gcc GCC_LPASS_SWAY_CLK>, 1188c2ecf20Sopenharmony_ci <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>, 1198c2ecf20Sopenharmony_ci <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>, 1208c2ecf20Sopenharmony_ci <&lpasscc LPASS_QDSP6SS_XO_CLK>, 1218c2ecf20Sopenharmony_ci <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>, 1228c2ecf20Sopenharmony_ci <&lpasscc LPASS_QDSP6SS_CORE_CLK>; 1238c2ecf20Sopenharmony_ci clock-names = "xo", "sway_cbcr", 1248c2ecf20Sopenharmony_ci "lpass_ahbs_aon_cbcr", 1258c2ecf20Sopenharmony_ci "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", 1268c2ecf20Sopenharmony_ci "qdsp6ss_sleep", "qdsp6ss_core"; 1278c2ecf20Sopenharmony_ci 1288c2ecf20Sopenharmony_ci power-domains = <&rpmhpd SDM845_CX>; 1298c2ecf20Sopenharmony_ci 1308c2ecf20Sopenharmony_ci resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>, 1318c2ecf20Sopenharmony_ci <&aoss_reset AOSS_CC_LPASS_RESTART>; 1328c2ecf20Sopenharmony_ci reset-names = "pdc_sync", "cc_lpass"; 1338c2ecf20Sopenharmony_ci 1348c2ecf20Sopenharmony_ci qcom,halt-regs = <&tcsr_mutex_regs 0x22000>; 1358c2ecf20Sopenharmony_ci 1368c2ecf20Sopenharmony_ci memory-region = <&pil_adsp_mem>; 1378c2ecf20Sopenharmony_ci 1388c2ecf20Sopenharmony_ci qcom,smem-states = <&adsp_smp2p_out 0>; 1398c2ecf20Sopenharmony_ci qcom,smem-state-names = "stop"; 1408c2ecf20Sopenharmony_ci }; 141