18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 28c2ecf20Sopenharmony_ci%YAML 1.2 38c2ecf20Sopenharmony_ci--- 48c2ecf20Sopenharmony_ci$id: "http://devicetree.org/schemas/remoteproc/ingenic,vpu.yaml#" 58c2ecf20Sopenharmony_ci$schema: "http://devicetree.org/meta-schemas/core.yaml#" 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_cititle: Ingenic Video Processing Unit bindings 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_cidescription: 108c2ecf20Sopenharmony_ci Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from 118c2ecf20Sopenharmony_ci Ingenic is a second Xburst MIPS CPU very similar to the main core. 128c2ecf20Sopenharmony_ci This document describes the devicetree bindings for this auxiliary 138c2ecf20Sopenharmony_ci processor. 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_cimaintainers: 168c2ecf20Sopenharmony_ci - Paul Cercueil <paul@crapouillou.net> 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciproperties: 198c2ecf20Sopenharmony_ci compatible: 208c2ecf20Sopenharmony_ci const: ingenic,jz4770-vpu-rproc 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci reg: 238c2ecf20Sopenharmony_ci items: 248c2ecf20Sopenharmony_ci - description: aux registers 258c2ecf20Sopenharmony_ci - description: tcsm0 registers 268c2ecf20Sopenharmony_ci - description: tcsm1 registers 278c2ecf20Sopenharmony_ci - description: sram registers 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci reg-names: 308c2ecf20Sopenharmony_ci items: 318c2ecf20Sopenharmony_ci - const: aux 328c2ecf20Sopenharmony_ci - const: tcsm0 338c2ecf20Sopenharmony_ci - const: tcsm1 348c2ecf20Sopenharmony_ci - const: sram 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_ci clocks: 378c2ecf20Sopenharmony_ci items: 388c2ecf20Sopenharmony_ci - description: aux clock 398c2ecf20Sopenharmony_ci - description: vpu clock 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci clock-names: 428c2ecf20Sopenharmony_ci items: 438c2ecf20Sopenharmony_ci - const: aux 448c2ecf20Sopenharmony_ci - const: vpu 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci interrupts: 478c2ecf20Sopenharmony_ci description: VPU hardware interrupt 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_cirequired: 508c2ecf20Sopenharmony_ci - compatible 518c2ecf20Sopenharmony_ci - reg 528c2ecf20Sopenharmony_ci - reg-names 538c2ecf20Sopenharmony_ci - clocks 548c2ecf20Sopenharmony_ci - clock-names 558c2ecf20Sopenharmony_ci - interrupts 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ciadditionalProperties: false 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ciexamples: 608c2ecf20Sopenharmony_ci - | 618c2ecf20Sopenharmony_ci #include <dt-bindings/clock/jz4770-cgu.h> 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci vpu: video-decoder@132a0000 { 648c2ecf20Sopenharmony_ci compatible = "ingenic,jz4770-vpu-rproc"; 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ci reg = <0x132a0000 0x20>, /* AUX */ 678c2ecf20Sopenharmony_ci <0x132b0000 0x4000>, /* TCSM0 */ 688c2ecf20Sopenharmony_ci <0x132c0000 0xc000>, /* TCSM1 */ 698c2ecf20Sopenharmony_ci <0x132f0000 0x7000>; /* SRAM */ 708c2ecf20Sopenharmony_ci reg-names = "aux", "tcsm0", "tcsm1", "sram"; 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci clocks = <&cgu JZ4770_CLK_AUX>, <&cgu JZ4770_CLK_VPU>; 738c2ecf20Sopenharmony_ci clock-names = "aux", "vpu"; 748c2ecf20Sopenharmony_ci 758c2ecf20Sopenharmony_ci interrupt-parent = <&cpuintc>; 768c2ecf20Sopenharmony_ci interrupts = <3>; 778c2ecf20Sopenharmony_ci }; 78