18c2ecf20Sopenharmony_ciDevicetree binding for regmap 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciOptional properties: 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci little-endian, 68c2ecf20Sopenharmony_ci big-endian, 78c2ecf20Sopenharmony_ci native-endian: See common-properties.txt for a definition 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciNote: 108c2ecf20Sopenharmony_ciRegmap defaults to little-endian register access on MMIO based 118c2ecf20Sopenharmony_cidevices, this is by far the most common setting. On CPU 128c2ecf20Sopenharmony_ciarchitectures that typically run big-endian operating systems 138c2ecf20Sopenharmony_ci(e.g. PowerPC), registers can be defined as big-endian and must 148c2ecf20Sopenharmony_cibe marked that way in the devicetree. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciOn SoCs that can be operated in both big-endian and little-endian 178c2ecf20Sopenharmony_cimodes, with a single hardware switch controlling both the endianness 188c2ecf20Sopenharmony_ciof the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS 198c2ecf20Sopenharmony_cichips), "native-endian" is used to allow using the same device tree 208c2ecf20Sopenharmony_ciblob in both cases. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ciExamples: 238c2ecf20Sopenharmony_ciScenario 1 : a register set in big-endian mode. 248c2ecf20Sopenharmony_cidev: dev@40031000 { 258c2ecf20Sopenharmony_ci compatible = "syscon"; 268c2ecf20Sopenharmony_ci reg = <0x40031000 0x1000>; 278c2ecf20Sopenharmony_ci big-endian; 288c2ecf20Sopenharmony_ci ... 298c2ecf20Sopenharmony_ci}; 30