18c2ecf20Sopenharmony_ciZTE ZX PWM controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci - compatible: Should be "zte,zx296718-pwm".
58c2ecf20Sopenharmony_ci - reg: Physical base address and length of the controller's registers.
68c2ecf20Sopenharmony_ci - clocks : The phandle and specifier referencing the controller's clocks.
78c2ecf20Sopenharmony_ci - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller.  The
88c2ecf20Sopenharmony_ci   PCLK is for register access, while WCLK is the reference clock for
98c2ecf20Sopenharmony_ci   calculating period and duty cycles.
108c2ecf20Sopenharmony_ci - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
118c2ecf20Sopenharmony_ci   the cells format.
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ciExample:
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci	pwm: pwm@1439000 {
168c2ecf20Sopenharmony_ci		compatible = "zte,zx296718-pwm";
178c2ecf20Sopenharmony_ci		reg = <0x1439000 0x1000>;
188c2ecf20Sopenharmony_ci		clocks = <&lsp1crm LSP1_PWM_PCLK>,
198c2ecf20Sopenharmony_ci			 <&lsp1crm LSP1_PWM_WCLK>;
208c2ecf20Sopenharmony_ci		clock-names = "pclk", "wclk";
218c2ecf20Sopenharmony_ci		#pwm-cells = <3>;
228c2ecf20Sopenharmony_ci	};
23