18c2ecf20Sopenharmony_ciTegra SoC PWFM controller
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38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible: Must be:
58c2ecf20Sopenharmony_ci  - "nvidia,tegra20-pwm": for Tegra20
68c2ecf20Sopenharmony_ci  - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
78c2ecf20Sopenharmony_ci  - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
88c2ecf20Sopenharmony_ci  - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
98c2ecf20Sopenharmony_ci  - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
108c2ecf20Sopenharmony_ci  - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
118c2ecf20Sopenharmony_ci  - "nvidia,tegra186-pwm": for Tegra186
128c2ecf20Sopenharmony_ci  - "nvidia,tegra194-pwm": for Tegra194
138c2ecf20Sopenharmony_ci- reg: physical base address and length of the controller's registers
148c2ecf20Sopenharmony_ci- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
158c2ecf20Sopenharmony_ci  the cells format.
168c2ecf20Sopenharmony_ci- clocks: Must contain one entry, for the module clock.
178c2ecf20Sopenharmony_ci  See ../clocks/clock-bindings.txt for details.
188c2ecf20Sopenharmony_ci- resets: Must contain an entry for each entry in reset-names.
198c2ecf20Sopenharmony_ci  See ../reset/reset.txt for details.
208c2ecf20Sopenharmony_ci- reset-names: Must include the following entries:
218c2ecf20Sopenharmony_ci  - pwm
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ciOptional properties:
248c2ecf20Sopenharmony_ci============================
258c2ecf20Sopenharmony_ciIn some of the interface like PWM based regulator device, it is required
268c2ecf20Sopenharmony_cito configure the pins differently in different states, especially in suspend
278c2ecf20Sopenharmony_cistate of the system. The configuration of pin is provided via the pinctrl
288c2ecf20Sopenharmony_ciDT node as detailed in the pinctrl DT binding document
298c2ecf20Sopenharmony_ci	Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
308c2ecf20Sopenharmony_ci
318c2ecf20Sopenharmony_ciThe PWM node will have following optional properties.
328c2ecf20Sopenharmony_cipinctrl-names:	Pin state names. Must be "default" and "sleep".
338c2ecf20Sopenharmony_cipinctrl-0:	phandle for the default/active state of pin configurations.
348c2ecf20Sopenharmony_cipinctrl-1:	phandle for the sleep state of pin configurations.
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368c2ecf20Sopenharmony_ciExample:
378c2ecf20Sopenharmony_ci
388c2ecf20Sopenharmony_ci	pwm: pwm@7000a000 {
398c2ecf20Sopenharmony_ci		compatible = "nvidia,tegra20-pwm";
408c2ecf20Sopenharmony_ci		reg = <0x7000a000 0x100>;
418c2ecf20Sopenharmony_ci		#pwm-cells = <2>;
428c2ecf20Sopenharmony_ci		clocks = <&tegra_car 17>;
438c2ecf20Sopenharmony_ci		resets = <&tegra_car 17>;
448c2ecf20Sopenharmony_ci		reset-names = "pwm";
458c2ecf20Sopenharmony_ci	};
468c2ecf20Sopenharmony_ci
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488c2ecf20Sopenharmony_ciExample with the pin configuration for suspend and resume:
498c2ecf20Sopenharmony_ci=========================================================
508c2ecf20Sopenharmony_ciSuppose pin PE7 (On Tegra210) interfaced with the regulator device and
518c2ecf20Sopenharmony_ciit requires PWM output to be tristated when system enters suspend.
528c2ecf20Sopenharmony_ciFollowing will be DT binding to achieve this:
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ci#include <dt-bindings/pinctrl/pinctrl-tegra.h>
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ci	pinmux@700008d4 {
578c2ecf20Sopenharmony_ci		pwm_active_state: pwm_active_state {
588c2ecf20Sopenharmony_ci                        pe7 {
598c2ecf20Sopenharmony_ci                                nvidia,pins = "pe7";
608c2ecf20Sopenharmony_ci                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
618c2ecf20Sopenharmony_ci			};
628c2ecf20Sopenharmony_ci		};
638c2ecf20Sopenharmony_ci
648c2ecf20Sopenharmony_ci		pwm_sleep_state: pwm_sleep_state {
658c2ecf20Sopenharmony_ci                        pe7 {
668c2ecf20Sopenharmony_ci                                nvidia,pins = "pe7";
678c2ecf20Sopenharmony_ci                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
688c2ecf20Sopenharmony_ci			};
698c2ecf20Sopenharmony_ci		};
708c2ecf20Sopenharmony_ci	};
718c2ecf20Sopenharmony_ci
728c2ecf20Sopenharmony_ci	pwm@7000a000 {
738c2ecf20Sopenharmony_ci		/* Mandatory PWM properties */
748c2ecf20Sopenharmony_ci		pinctrl-names = "default", "sleep";
758c2ecf20Sopenharmony_ci		pinctrl-0 = <&pwm_active_state>;
768c2ecf20Sopenharmony_ci		pinctrl-1 = <&pwm_sleep_state>;
778c2ecf20Sopenharmony_ci	};
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