18c2ecf20Sopenharmony_ci* Freescale QorIQ 1588 timer based PTP clock
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciGeneral Properties:
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ci  - compatible   Should be "fsl,etsec-ptp" for eTSEC
68c2ecf20Sopenharmony_ci                 Should be "fsl,fman-ptp-timer" for DPAA FMan
78c2ecf20Sopenharmony_ci                 Should be "fsl,dpaa2-ptp" for DPAA2
88c2ecf20Sopenharmony_ci                 Should be "fsl,enetc-ptp" for ENETC
98c2ecf20Sopenharmony_ci  - reg          Offset and length of the register set for the device
108c2ecf20Sopenharmony_ci  - interrupts   There should be at least two interrupts. Some devices
118c2ecf20Sopenharmony_ci                 have as many as four PTP related interrupts.
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ciClock Properties:
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci  - fsl,cksel        Timer reference clock source.
168c2ecf20Sopenharmony_ci  - fsl,tclk-period  Timer reference clock period in nanoseconds.
178c2ecf20Sopenharmony_ci  - fsl,tmr-prsc     Prescaler, divides the output clock.
188c2ecf20Sopenharmony_ci  - fsl,tmr-add      Frequency compensation value.
198c2ecf20Sopenharmony_ci  - fsl,tmr-fiper1   Fixed interval period pulse generator.
208c2ecf20Sopenharmony_ci  - fsl,tmr-fiper2   Fixed interval period pulse generator.
218c2ecf20Sopenharmony_ci  - fsl,tmr-fiper3   Fixed interval period pulse generator.
228c2ecf20Sopenharmony_ci                     Supported only on DPAA2 and ENETC hardware.
238c2ecf20Sopenharmony_ci  - fsl,max-adj      Maximum frequency adjustment in parts per billion.
248c2ecf20Sopenharmony_ci  - fsl,extts-fifo   The presence of this property indicates hardware
258c2ecf20Sopenharmony_ci		     support for the external trigger stamp FIFO.
268c2ecf20Sopenharmony_ci  - little-endian    The presence of this property indicates the 1588 timer
278c2ecf20Sopenharmony_ci		     IP block is little-endian mode. The default endian mode
288c2ecf20Sopenharmony_ci		     is big-endian.
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci  These properties set the operational parameters for the PTP
318c2ecf20Sopenharmony_ci  clock. You must choose these carefully for the clock to work right.
328c2ecf20Sopenharmony_ci  Here is how to figure good values:
338c2ecf20Sopenharmony_ci
348c2ecf20Sopenharmony_ci  TimerOsc     = selected reference clock   MHz
358c2ecf20Sopenharmony_ci  tclk_period  = desired clock period       nanoseconds
368c2ecf20Sopenharmony_ci  NominalFreq  = 1000 / tclk_period         MHz
378c2ecf20Sopenharmony_ci  FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
388c2ecf20Sopenharmony_ci  tmr_add      = ceil(2^32 / FreqDivRatio)
398c2ecf20Sopenharmony_ci  OutputClock  = NominalFreq / tmr_prsc     MHz
408c2ecf20Sopenharmony_ci  PulseWidth   = 1 / OutputClock            microseconds
418c2ecf20Sopenharmony_ci  FiperFreq1   = desired frequency in Hz
428c2ecf20Sopenharmony_ci  FiperDiv1    = 1000000 * OutputClock / FiperFreq1
438c2ecf20Sopenharmony_ci  tmr_fiper1   = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
448c2ecf20Sopenharmony_ci  max_adj      = 1000000000 * (FreqDivRatio - 1.0) - 1
458c2ecf20Sopenharmony_ci
468c2ecf20Sopenharmony_ci  The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
478c2ecf20Sopenharmony_ci  driver expects that tmr_fiper1 will be correctly set to produce a 1
488c2ecf20Sopenharmony_ci  Pulse Per Second (PPS) signal, since this will be offered to the PPS
498c2ecf20Sopenharmony_ci  subsystem to synchronize the Linux clock.
508c2ecf20Sopenharmony_ci
518c2ecf20Sopenharmony_ci  Reference clock source is determined by the value, which is holded
528c2ecf20Sopenharmony_ci  in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
538c2ecf20Sopenharmony_ci  value, which will be directly written in those bits, that is why,
548c2ecf20Sopenharmony_ci  according to reference manual, the next clock sources can be used:
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ci  For eTSEC,
578c2ecf20Sopenharmony_ci  <0> - external high precision timer reference clock (TSEC_TMR_CLK
588c2ecf20Sopenharmony_ci        input is used for this purpose);
598c2ecf20Sopenharmony_ci  <1> - eTSEC system clock;
608c2ecf20Sopenharmony_ci  <2> - eTSEC1 transmit clock;
618c2ecf20Sopenharmony_ci  <3> - RTC clock input.
628c2ecf20Sopenharmony_ci
638c2ecf20Sopenharmony_ci  For DPAA FMan,
648c2ecf20Sopenharmony_ci  <0> - external high precision timer reference clock (TMR_1588_CLK)
658c2ecf20Sopenharmony_ci  <1> - MAC system clock (1/2 FMan clock)
668c2ecf20Sopenharmony_ci  <2> - reserved
678c2ecf20Sopenharmony_ci  <3> - RTC clock oscillator
688c2ecf20Sopenharmony_ci
698c2ecf20Sopenharmony_ci  When this attribute is not used, the IEEE 1588 timer reference clock
708c2ecf20Sopenharmony_ci  will use the eTSEC system clock (for Gianfar) or the MAC system
718c2ecf20Sopenharmony_ci  clock (for DPAA).
728c2ecf20Sopenharmony_ci
738c2ecf20Sopenharmony_ciExample:
748c2ecf20Sopenharmony_ci
758c2ecf20Sopenharmony_ci	ptp_clock@24e00 {
768c2ecf20Sopenharmony_ci		compatible = "fsl,etsec-ptp";
778c2ecf20Sopenharmony_ci		reg = <0x24E00 0xB0>;
788c2ecf20Sopenharmony_ci		interrupts = <12 0x8 13 0x8>;
798c2ecf20Sopenharmony_ci		interrupt-parent = < &ipic >;
808c2ecf20Sopenharmony_ci		fsl,cksel       = <1>;
818c2ecf20Sopenharmony_ci		fsl,tclk-period = <10>;
828c2ecf20Sopenharmony_ci		fsl,tmr-prsc    = <100>;
838c2ecf20Sopenharmony_ci		fsl,tmr-add     = <0x999999A4>;
848c2ecf20Sopenharmony_ci		fsl,tmr-fiper1  = <0x3B9AC9F6>;
858c2ecf20Sopenharmony_ci		fsl,tmr-fiper2  = <0x00018696>;
868c2ecf20Sopenharmony_ci		fsl,max-adj     = <659999998>;
878c2ecf20Sopenharmony_ci	};
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