18c2ecf20Sopenharmony_ci* Power Management Controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciProperties: 48c2ecf20Sopenharmony_ci- compatible: "fsl,<chip>-pmc". 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci "fsl,mpc8349-pmc" should be listed for any chip whose PMC is 78c2ecf20Sopenharmony_ci compatible. "fsl,mpc8313-pmc" should also be listed for any chip 88c2ecf20Sopenharmony_ci whose PMC is compatible, and implies deep-sleep capability. 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci "fsl,mpc8548-pmc" should be listed for any chip whose PMC is 118c2ecf20Sopenharmony_ci compatible. "fsl,mpc8536-pmc" should also be listed for any chip 128c2ecf20Sopenharmony_ci whose PMC is compatible, and implies deep-sleep capability. 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is 158c2ecf20Sopenharmony_ci compatible; all statements below that apply to "fsl,mpc8548-pmc" also 168c2ecf20Sopenharmony_ci apply to "fsl,mpc8641d-pmc". 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these 198c2ecf20Sopenharmony_ci bit assignments are indicated via the sleep specifier in each device's 208c2ecf20Sopenharmony_ci sleep property. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource 238c2ecf20Sopenharmony_ci is the PMC block, and the second resource is the Clock Configuration 248c2ecf20Sopenharmony_ci block. 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci For devices compatible with "fsl,mpc8548-pmc", the first resource 278c2ecf20Sopenharmony_ci is a 32-byte block beginning with DEVDISR. 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first 308c2ecf20Sopenharmony_ci resource is the PMC block interrupt. 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices, 338c2ecf20Sopenharmony_ci this is a phandle to an "fsl,gtm" node on which timer 4 can be used as 348c2ecf20Sopenharmony_ci a wakeup source from deep sleep. 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_ciSleep specifiers: 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit 398c2ecf20Sopenharmony_ci that is set in the cell, the corresponding bit in SCCR will be saved 408c2ecf20Sopenharmony_ci and cleared on suspend, and restored on resume. This sleep controller 418c2ecf20Sopenharmony_ci supports disabling and resuming devices at any time. 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of 448c2ecf20Sopenharmony_ci which will be ORed into PMCDR upon suspend, and cleared from PMCDR 458c2ecf20Sopenharmony_ci upon resume. The first two cells are as described for fsl,mpc8578-pmc. 468c2ecf20Sopenharmony_ci This sleep controller only supports disabling devices during system 478c2ecf20Sopenharmony_ci sleep, or permanently. 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the 508c2ecf20Sopenharmony_ci first of which will be ORed into DEVDISR (and the second into 518c2ecf20Sopenharmony_ci DEVDISR2, if present -- this cell should be zero or absent if the 528c2ecf20Sopenharmony_ci hardware does not have DEVDISR2) upon a request for permanent device 538c2ecf20Sopenharmony_ci disabling. This sleep controller does not support configuring devices 548c2ecf20Sopenharmony_ci to disable during system sleep (unless supported by another compatible 558c2ecf20Sopenharmony_ci match), or dynamically. 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ciExample: 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ci power@b00 { 608c2ecf20Sopenharmony_ci compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; 618c2ecf20Sopenharmony_ci reg = <0xb00 0x100 0xa00 0x100>; 628c2ecf20Sopenharmony_ci interrupts = <80 8>; 638c2ecf20Sopenharmony_ci }; 64