18c2ecf20Sopenharmony_ci* Freescale MPIC timers 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci- compatible: "fsl,mpic-global-timer" 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci- reg : Contains two regions. The first is the main timer register bank 78c2ecf20Sopenharmony_ci (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control 88c2ecf20Sopenharmony_ci register (TCRx) for the group. 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci- fsl,available-ranges: use <start count> style section to define which 118c2ecf20Sopenharmony_ci timer interrupts can be used. This property is optional; without this, 128c2ecf20Sopenharmony_ci all timers within the group can be used. 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci- interrupts: one interrupt per timer in the group, in order, starting 158c2ecf20Sopenharmony_ci with timer zero. If timer-available-ranges is present, only the 168c2ecf20Sopenharmony_ci interrupts that correspond to available timers shall be present. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciExample: 198c2ecf20Sopenharmony_ci /* Note that this requires #interrupt-cells to be 4 */ 208c2ecf20Sopenharmony_ci timer0: timer@41100 { 218c2ecf20Sopenharmony_ci compatible = "fsl,mpic-global-timer"; 228c2ecf20Sopenharmony_ci reg = <0x41100 0x100 0x41300 4>; 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci /* Another AMP partition is using timers 0 and 1 */ 258c2ecf20Sopenharmony_ci fsl,available-ranges = <2 2>; 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci interrupts = <2 0 3 0 288c2ecf20Sopenharmony_ci 3 0 3 0>; 298c2ecf20Sopenharmony_ci }; 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci timer1: timer@42100 { 328c2ecf20Sopenharmony_ci compatible = "fsl,mpic-global-timer"; 338c2ecf20Sopenharmony_ci reg = <0x42100 0x100 0x42300 4>; 348c2ecf20Sopenharmony_ci interrupts = <4 0 3 0 358c2ecf20Sopenharmony_ci 5 0 3 0 368c2ecf20Sopenharmony_ci 6 0 3 0 378c2ecf20Sopenharmony_ci 7 0 3 0>; 388c2ecf20Sopenharmony_ci }; 39