18c2ecf20Sopenharmony_ci* FSL MPIC Message Registers 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis binding specifies what properties must be available in the device tree 48c2ecf20Sopenharmony_cirepresentation of the message register blocks found in some FSL MPIC 58c2ecf20Sopenharmony_ciimplementations. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci - compatible: Specifies the compatibility list for the message register 108c2ecf20Sopenharmony_ci block. The type shall be <string-list> and the value shall be of the form 118c2ecf20Sopenharmony_ci "fsl,mpic-v<version>-msgr", where <version> is the version number of 128c2ecf20Sopenharmony_ci the MPIC containing the message registers. 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci - reg: Specifies the base physical address(s) and size(s) of the 158c2ecf20Sopenharmony_ci message register block's addressable register space. The type shall be 168c2ecf20Sopenharmony_ci <prop-encoded-array>. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci - interrupts: Specifies a list of interrupt-specifiers which are available 198c2ecf20Sopenharmony_ci for receiving interrupts. Interrupt-specifier consists of two cells: first 208c2ecf20Sopenharmony_ci cell is interrupt-number and second cell is level-sense. The type shall be 218c2ecf20Sopenharmony_ci <prop-encoded-array>. 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ciOptional properties: 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci - mpic-msgr-receive-mask: Specifies what registers in the containing block 268c2ecf20Sopenharmony_ci are allowed to receive interrupts. The value is a bit mask where a set 278c2ecf20Sopenharmony_ci bit at bit 'n' indicates that message register 'n' can receive interrupts. 288c2ecf20Sopenharmony_ci Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall 298c2ecf20Sopenharmony_ci be <u32>. If not present, then all of the message registers in the block 308c2ecf20Sopenharmony_ci are available. 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ciAliases: 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci An alias should be created for every message register block. They are not 358c2ecf20Sopenharmony_ci required, though. However, a particular implementation of this binding 368c2ecf20Sopenharmony_ci may require aliases to be present. Aliases are of the form 378c2ecf20Sopenharmony_ci 'mpic-msgr-block<n>', where <n> is an integer specifying the block's number. 388c2ecf20Sopenharmony_ci Numbers shall start at 0. 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ciExample: 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci aliases { 438c2ecf20Sopenharmony_ci mpic-msgr-block0 = &mpic_msgr_block0; 448c2ecf20Sopenharmony_ci mpic-msgr-block1 = &mpic_msgr_block1; 458c2ecf20Sopenharmony_ci }; 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci mpic_msgr_block0: mpic-msgr-block@41400 { 488c2ecf20Sopenharmony_ci compatible = "fsl,mpic-v3.1-msgr"; 498c2ecf20Sopenharmony_ci reg = <0x41400 0x200>; 508c2ecf20Sopenharmony_ci // Message registers 0 and 2 in this block can receive interrupts on 518c2ecf20Sopenharmony_ci // sources 0xb0 and 0xb2, respectively. 528c2ecf20Sopenharmony_ci interrupts = <0xb0 2 0xb2 2>; 538c2ecf20Sopenharmony_ci mpic-msgr-receive-mask = <0x5>; 548c2ecf20Sopenharmony_ci }; 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci mpic_msgr_block1: mpic-msgr-block@42400 { 578c2ecf20Sopenharmony_ci compatible = "fsl,mpic-v3.1-msgr"; 588c2ecf20Sopenharmony_ci reg = <0x42400 0x200>; 598c2ecf20Sopenharmony_ci // Message registers 0 and 2 in this block can receive interrupts on 608c2ecf20Sopenharmony_ci // sources 0xb4 and 0xb6, respectively. 618c2ecf20Sopenharmony_ci interrupts = <0xb4 2 0xb6 2>; 628c2ecf20Sopenharmony_ci mpic-msgr-receive-mask = <0x5>; 638c2ecf20Sopenharmony_ci }; 64