18c2ecf20Sopenharmony_ci* Freescale DMA Controllers 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ci** Freescale Elo DMA Controller 48c2ecf20Sopenharmony_ci This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx 58c2ecf20Sopenharmony_ci series chips such as mpc8315, mpc8349, mpc8379 etc. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci- compatible : must include "fsl,elo-dma" 108c2ecf20Sopenharmony_ci- reg : DMA General Status Register, i.e. DGSR which contains 118c2ecf20Sopenharmony_ci status for all the 4 DMA channels 128c2ecf20Sopenharmony_ci- ranges : describes the mapping between the address space of the 138c2ecf20Sopenharmony_ci DMA channels and the address space of the DMA controller 148c2ecf20Sopenharmony_ci- cell-index : controller index. 0 for controller @ 0x8100 158c2ecf20Sopenharmony_ci- interrupts : interrupt specifier for DMA IRQ 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci- DMA channel nodes: 188c2ecf20Sopenharmony_ci - compatible : must include "fsl,elo-dma-channel" 198c2ecf20Sopenharmony_ci However, see note below. 208c2ecf20Sopenharmony_ci - reg : DMA channel specific registers 218c2ecf20Sopenharmony_ci - cell-index : DMA channel index starts at 0. 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ciOptional properties: 248c2ecf20Sopenharmony_ci - interrupts : interrupt specifier for DMA channel IRQ 258c2ecf20Sopenharmony_ci (on 83xx this is expected to be identical to 268c2ecf20Sopenharmony_ci the interrupts property of the parent node) 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ciExample: 298c2ecf20Sopenharmony_ci dma@82a8 { 308c2ecf20Sopenharmony_ci #address-cells = <1>; 318c2ecf20Sopenharmony_ci #size-cells = <1>; 328c2ecf20Sopenharmony_ci compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; 338c2ecf20Sopenharmony_ci reg = <0x82a8 4>; 348c2ecf20Sopenharmony_ci ranges = <0 0x8100 0x1a4>; 358c2ecf20Sopenharmony_ci interrupt-parent = <&ipic>; 368c2ecf20Sopenharmony_ci interrupts = <71 8>; 378c2ecf20Sopenharmony_ci cell-index = <0>; 388c2ecf20Sopenharmony_ci dma-channel@0 { 398c2ecf20Sopenharmony_ci compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 408c2ecf20Sopenharmony_ci cell-index = <0>; 418c2ecf20Sopenharmony_ci reg = <0 0x80>; 428c2ecf20Sopenharmony_ci interrupt-parent = <&ipic>; 438c2ecf20Sopenharmony_ci interrupts = <71 8>; 448c2ecf20Sopenharmony_ci }; 458c2ecf20Sopenharmony_ci dma-channel@80 { 468c2ecf20Sopenharmony_ci compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 478c2ecf20Sopenharmony_ci cell-index = <1>; 488c2ecf20Sopenharmony_ci reg = <0x80 0x80>; 498c2ecf20Sopenharmony_ci interrupt-parent = <&ipic>; 508c2ecf20Sopenharmony_ci interrupts = <71 8>; 518c2ecf20Sopenharmony_ci }; 528c2ecf20Sopenharmony_ci dma-channel@100 { 538c2ecf20Sopenharmony_ci compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 548c2ecf20Sopenharmony_ci cell-index = <2>; 558c2ecf20Sopenharmony_ci reg = <0x100 0x80>; 568c2ecf20Sopenharmony_ci interrupt-parent = <&ipic>; 578c2ecf20Sopenharmony_ci interrupts = <71 8>; 588c2ecf20Sopenharmony_ci }; 598c2ecf20Sopenharmony_ci dma-channel@180 { 608c2ecf20Sopenharmony_ci compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 618c2ecf20Sopenharmony_ci cell-index = <3>; 628c2ecf20Sopenharmony_ci reg = <0x180 0x80>; 638c2ecf20Sopenharmony_ci interrupt-parent = <&ipic>; 648c2ecf20Sopenharmony_ci interrupts = <71 8>; 658c2ecf20Sopenharmony_ci }; 668c2ecf20Sopenharmony_ci }; 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci** Freescale EloPlus DMA Controller 698c2ecf20Sopenharmony_ci This is a 4-channel DMA controller with extended addresses and chaining, 708c2ecf20Sopenharmony_ci mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as 718c2ecf20Sopenharmony_ci mpc8540, mpc8641 p4080, bsc9131 etc. 728c2ecf20Sopenharmony_ci 738c2ecf20Sopenharmony_ciRequired properties: 748c2ecf20Sopenharmony_ci 758c2ecf20Sopenharmony_ci- compatible : must include "fsl,eloplus-dma" 768c2ecf20Sopenharmony_ci- reg : DMA General Status Register, i.e. DGSR which contains 778c2ecf20Sopenharmony_ci status for all the 4 DMA channels 788c2ecf20Sopenharmony_ci- cell-index : controller index. 0 for controller @ 0x21000, 798c2ecf20Sopenharmony_ci 1 for controller @ 0xc000 808c2ecf20Sopenharmony_ci- ranges : describes the mapping between the address space of the 818c2ecf20Sopenharmony_ci DMA channels and the address space of the DMA controller 828c2ecf20Sopenharmony_ci 838c2ecf20Sopenharmony_ci- DMA channel nodes: 848c2ecf20Sopenharmony_ci - compatible : must include "fsl,eloplus-dma-channel" 858c2ecf20Sopenharmony_ci However, see note below. 868c2ecf20Sopenharmony_ci - cell-index : DMA channel index starts at 0. 878c2ecf20Sopenharmony_ci - reg : DMA channel specific registers 888c2ecf20Sopenharmony_ci - interrupts : interrupt specifier for DMA channel IRQ 898c2ecf20Sopenharmony_ci 908c2ecf20Sopenharmony_ciExample: 918c2ecf20Sopenharmony_ci dma@21300 { 928c2ecf20Sopenharmony_ci #address-cells = <1>; 938c2ecf20Sopenharmony_ci #size-cells = <1>; 948c2ecf20Sopenharmony_ci compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; 958c2ecf20Sopenharmony_ci reg = <0x21300 4>; 968c2ecf20Sopenharmony_ci ranges = <0 0x21100 0x200>; 978c2ecf20Sopenharmony_ci cell-index = <0>; 988c2ecf20Sopenharmony_ci dma-channel@0 { 998c2ecf20Sopenharmony_ci compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 1008c2ecf20Sopenharmony_ci reg = <0 0x80>; 1018c2ecf20Sopenharmony_ci cell-index = <0>; 1028c2ecf20Sopenharmony_ci interrupt-parent = <&mpic>; 1038c2ecf20Sopenharmony_ci interrupts = <20 2>; 1048c2ecf20Sopenharmony_ci }; 1058c2ecf20Sopenharmony_ci dma-channel@80 { 1068c2ecf20Sopenharmony_ci compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 1078c2ecf20Sopenharmony_ci reg = <0x80 0x80>; 1088c2ecf20Sopenharmony_ci cell-index = <1>; 1098c2ecf20Sopenharmony_ci interrupt-parent = <&mpic>; 1108c2ecf20Sopenharmony_ci interrupts = <21 2>; 1118c2ecf20Sopenharmony_ci }; 1128c2ecf20Sopenharmony_ci dma-channel@100 { 1138c2ecf20Sopenharmony_ci compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 1148c2ecf20Sopenharmony_ci reg = <0x100 0x80>; 1158c2ecf20Sopenharmony_ci cell-index = <2>; 1168c2ecf20Sopenharmony_ci interrupt-parent = <&mpic>; 1178c2ecf20Sopenharmony_ci interrupts = <22 2>; 1188c2ecf20Sopenharmony_ci }; 1198c2ecf20Sopenharmony_ci dma-channel@180 { 1208c2ecf20Sopenharmony_ci compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 1218c2ecf20Sopenharmony_ci reg = <0x180 0x80>; 1228c2ecf20Sopenharmony_ci cell-index = <3>; 1238c2ecf20Sopenharmony_ci interrupt-parent = <&mpic>; 1248c2ecf20Sopenharmony_ci interrupts = <23 2>; 1258c2ecf20Sopenharmony_ci }; 1268c2ecf20Sopenharmony_ci }; 1278c2ecf20Sopenharmony_ci 1288c2ecf20Sopenharmony_ci** Freescale Elo3 DMA Controller 1298c2ecf20Sopenharmony_ci DMA controller which has same function as EloPlus except that Elo3 has 8 1308c2ecf20Sopenharmony_ci channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx 1318c2ecf20Sopenharmony_ci series chips, such as t1040, t4240, b4860. 1328c2ecf20Sopenharmony_ci 1338c2ecf20Sopenharmony_ciRequired properties: 1348c2ecf20Sopenharmony_ci 1358c2ecf20Sopenharmony_ci- compatible : must include "fsl,elo3-dma" 1368c2ecf20Sopenharmony_ci- reg : contains two entries for DMA General Status Registers, 1378c2ecf20Sopenharmony_ci i.e. DGSR0 which includes status for channel 1~4, and 1388c2ecf20Sopenharmony_ci DGSR1 for channel 5~8 1398c2ecf20Sopenharmony_ci- ranges : describes the mapping between the address space of the 1408c2ecf20Sopenharmony_ci DMA channels and the address space of the DMA controller 1418c2ecf20Sopenharmony_ci 1428c2ecf20Sopenharmony_ci- DMA channel nodes: 1438c2ecf20Sopenharmony_ci - compatible : must include "fsl,eloplus-dma-channel" 1448c2ecf20Sopenharmony_ci - reg : DMA channel specific registers 1458c2ecf20Sopenharmony_ci - interrupts : interrupt specifier for DMA channel IRQ 1468c2ecf20Sopenharmony_ci 1478c2ecf20Sopenharmony_ciExample: 1488c2ecf20Sopenharmony_cidma@100300 { 1498c2ecf20Sopenharmony_ci #address-cells = <1>; 1508c2ecf20Sopenharmony_ci #size-cells = <1>; 1518c2ecf20Sopenharmony_ci compatible = "fsl,elo3-dma"; 1528c2ecf20Sopenharmony_ci reg = <0x100300 0x4>, 1538c2ecf20Sopenharmony_ci <0x100600 0x4>; 1548c2ecf20Sopenharmony_ci ranges = <0x0 0x100100 0x500>; 1558c2ecf20Sopenharmony_ci dma-channel@0 { 1568c2ecf20Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 1578c2ecf20Sopenharmony_ci reg = <0x0 0x80>; 1588c2ecf20Sopenharmony_ci interrupts = <28 2 0 0>; 1598c2ecf20Sopenharmony_ci }; 1608c2ecf20Sopenharmony_ci dma-channel@80 { 1618c2ecf20Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 1628c2ecf20Sopenharmony_ci reg = <0x80 0x80>; 1638c2ecf20Sopenharmony_ci interrupts = <29 2 0 0>; 1648c2ecf20Sopenharmony_ci }; 1658c2ecf20Sopenharmony_ci dma-channel@100 { 1668c2ecf20Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 1678c2ecf20Sopenharmony_ci reg = <0x100 0x80>; 1688c2ecf20Sopenharmony_ci interrupts = <30 2 0 0>; 1698c2ecf20Sopenharmony_ci }; 1708c2ecf20Sopenharmony_ci dma-channel@180 { 1718c2ecf20Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 1728c2ecf20Sopenharmony_ci reg = <0x180 0x80>; 1738c2ecf20Sopenharmony_ci interrupts = <31 2 0 0>; 1748c2ecf20Sopenharmony_ci }; 1758c2ecf20Sopenharmony_ci dma-channel@300 { 1768c2ecf20Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 1778c2ecf20Sopenharmony_ci reg = <0x300 0x80>; 1788c2ecf20Sopenharmony_ci interrupts = <76 2 0 0>; 1798c2ecf20Sopenharmony_ci }; 1808c2ecf20Sopenharmony_ci dma-channel@380 { 1818c2ecf20Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 1828c2ecf20Sopenharmony_ci reg = <0x380 0x80>; 1838c2ecf20Sopenharmony_ci interrupts = <77 2 0 0>; 1848c2ecf20Sopenharmony_ci }; 1858c2ecf20Sopenharmony_ci dma-channel@400 { 1868c2ecf20Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 1878c2ecf20Sopenharmony_ci reg = <0x400 0x80>; 1888c2ecf20Sopenharmony_ci interrupts = <78 2 0 0>; 1898c2ecf20Sopenharmony_ci }; 1908c2ecf20Sopenharmony_ci dma-channel@480 { 1918c2ecf20Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 1928c2ecf20Sopenharmony_ci reg = <0x480 0x80>; 1938c2ecf20Sopenharmony_ci interrupts = <79 2 0 0>; 1948c2ecf20Sopenharmony_ci }; 1958c2ecf20Sopenharmony_ci}; 1968c2ecf20Sopenharmony_ci 1978c2ecf20Sopenharmony_ciNote on DMA channel compatible properties: The compatible property must say 1988c2ecf20Sopenharmony_ci"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA 1998c2ecf20Sopenharmony_cidriver (fsldma). Any DMA channel used by fsldma cannot be used by another 2008c2ecf20Sopenharmony_ciDMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA 2018c2ecf20Sopenharmony_cichannel that should be used for another driver should not use 2028c2ecf20Sopenharmony_ci"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for 2038c2ecf20Sopenharmony_ciexample, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt 2048c2ecf20Sopenharmony_cifor more information. 205