18c2ecf20Sopenharmony_ci===================================================================
28c2ecf20Sopenharmony_ciPower Architecture CPU Binding
38c2ecf20Sopenharmony_ciCopyright 2013 Freescale Semiconductor Inc.
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ciPower Architecture CPUs in Freescale SOCs are represented in device trees as
68c2ecf20Sopenharmony_ciper the definition in the Devicetree Specification.
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ciIn addition to the the Devicetree Specification definitions, the properties
98c2ecf20Sopenharmony_cidefined below may be present on CPU nodes.
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ciPROPERTIES
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ci   - fsl,eref-*
148c2ecf20Sopenharmony_ci        Usage: optional
158c2ecf20Sopenharmony_ci        Value type: <empty>
168c2ecf20Sopenharmony_ci        Definition: The EREF (EREF: A Programmer.s Reference Manual for
178c2ecf20Sopenharmony_ci	Freescale Power Architecture) defines the architecture for Freescale
188c2ecf20Sopenharmony_ci	Power CPUs.  The EREF defines some architecture categories not defined
198c2ecf20Sopenharmony_ci	by the Power ISA.  For these EREF-specific categories, the existence of
208c2ecf20Sopenharmony_ci	a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
218c2ecf20Sopenharmony_ci	name with all uppercase letters converted to lowercase, indicates that
228c2ecf20Sopenharmony_ci	the category is supported by the implementation.
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ci    - fsl,portid-mapping
258c2ecf20Sopenharmony_ci	Usage: optional
268c2ecf20Sopenharmony_ci	Value type: <u32>
278c2ecf20Sopenharmony_ci	Definition: The Coherency Subdomain ID Port Mapping Registers and
288c2ecf20Sopenharmony_ci	Snoop ID Port Mapping registers, which are part of the CoreNet
298c2ecf20Sopenharmony_ci	Coherency fabric (CCF), provide a CoreNet Coherency Subdomain
308c2ecf20Sopenharmony_ci	ID/CoreNet Snoop ID to cpu mapping functions.  Certain bits from
318c2ecf20Sopenharmony_ci	these registers should be set if the coresponding CPU should be
328c2ecf20Sopenharmony_ci	snooped.  This property defines a bitmask which selects the bit
338c2ecf20Sopenharmony_ci	that should be set if this cpu should be snooped.
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