18c2ecf20Sopenharmony_ci* Freescale PQ3 and QorIQ based Cache SRAM 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciFreescale's mpc85xx and some QorIQ platforms provide an 48c2ecf20Sopenharmony_cioption of configuring a part of (or full) cache memory 58c2ecf20Sopenharmony_cias SRAM. This cache SRAM representation in the device 68c2ecf20Sopenharmony_citree should be done as under:- 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciRequired properties: 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci- compatible : should be "fsl,p2020-cache-sram" 118c2ecf20Sopenharmony_ci- fsl,cache-sram-ctlr-handle : points to the L2 controller 128c2ecf20Sopenharmony_ci- reg : offset and length of the cache-sram. 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ciExample: 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_cicache-sram@fff00000 { 178c2ecf20Sopenharmony_ci fsl,cache-sram-ctlr-handle = <&L2>; 188c2ecf20Sopenharmony_ci reg = <0 0xfff00000 0 0x10000>; 198c2ecf20Sopenharmony_ci compatible = "fsl,p2020-cache-sram"; 208c2ecf20Sopenharmony_ci}; 21