18c2ecf20Sopenharmony_ciPPC4xx Clock Power Management (CPM) node 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci - compatible : compatible list, currently only "ibm,cpm" 58c2ecf20Sopenharmony_ci - dcr-access-method : "native" 68c2ecf20Sopenharmony_ci - dcr-reg : < DCR register range > 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciOptional properties: 98c2ecf20Sopenharmony_ci - er-offset : All 4xx SoCs with a CPM controller have 108c2ecf20Sopenharmony_ci one of two different order for the CPM 118c2ecf20Sopenharmony_ci registers. Some have the CPM registers 128c2ecf20Sopenharmony_ci in the following order (ER,FR,SR). The 138c2ecf20Sopenharmony_ci others have them in the following order 148c2ecf20Sopenharmony_ci (SR,ER,FR). For the second case set 158c2ecf20Sopenharmony_ci er-offset = <1>. 168c2ecf20Sopenharmony_ci - unused-units : specifier consist of one cell. For each 178c2ecf20Sopenharmony_ci bit in the cell, the corresponding bit 188c2ecf20Sopenharmony_ci in CPM will be set to turn off unused 198c2ecf20Sopenharmony_ci devices. 208c2ecf20Sopenharmony_ci - idle-doze : specifier consist of one cell. For each 218c2ecf20Sopenharmony_ci bit in the cell, the corresponding bit 228c2ecf20Sopenharmony_ci in CPM will be set to turn off unused 238c2ecf20Sopenharmony_ci devices. This is usually just CPM[CPU]. 248c2ecf20Sopenharmony_ci - standby : specifier consist of one cell. For each 258c2ecf20Sopenharmony_ci bit in the cell, the corresponding bit 268c2ecf20Sopenharmony_ci in CPM will be set on standby and 278c2ecf20Sopenharmony_ci restored on resume. 288c2ecf20Sopenharmony_ci - suspend : specifier consist of one cell. For each 298c2ecf20Sopenharmony_ci bit in the cell, the corresponding bit 308c2ecf20Sopenharmony_ci in CPM will be set on suspend (mem) and 318c2ecf20Sopenharmony_ci restored on resume. Note, for standby 328c2ecf20Sopenharmony_ci and suspend the corresponding bits can 338c2ecf20Sopenharmony_ci be different or the same. Usually for 348c2ecf20Sopenharmony_ci standby only class 2 and 3 units are set. 358c2ecf20Sopenharmony_ci However, the interface does not care. 368c2ecf20Sopenharmony_ci If they are the same, the additional 378c2ecf20Sopenharmony_ci power saving will be seeing if support 388c2ecf20Sopenharmony_ci is available to put the DDR in self 398c2ecf20Sopenharmony_ci refresh mode and any additional power 408c2ecf20Sopenharmony_ci saving techniques for the specific SoC. 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ciExample: 438c2ecf20Sopenharmony_ci CPM0: cpm { 448c2ecf20Sopenharmony_ci compatible = "ibm,cpm"; 458c2ecf20Sopenharmony_ci dcr-access-method = "native"; 468c2ecf20Sopenharmony_ci dcr-reg = <0x160 0x003>; 478c2ecf20Sopenharmony_ci er-offset = <0>; 488c2ecf20Sopenharmony_ci unused-units = <0x00000100>; 498c2ecf20Sopenharmony_ci idle-doze = <0x02000000>; 508c2ecf20Sopenharmony_ci standby = <0xfeff0000>; 518c2ecf20Sopenharmony_ci suspend = <0xfeff791d>; 528c2ecf20Sopenharmony_ci}; 53