18c2ecf20Sopenharmony_ci* Spreadtrum Pin Controller
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38c2ecf20Sopenharmony_ciThe Spreadtrum pin controller are organized in 3 blocks (types).
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58c2ecf20Sopenharmony_ciThe first block comprises some global control registers, and each
68c2ecf20Sopenharmony_ciregister contains several bit fields with one bit or several bits
78c2ecf20Sopenharmony_cito configure for some global common configuration, such as domain
88c2ecf20Sopenharmony_cipad driving level, system control select and so on ("domain pad
98c2ecf20Sopenharmony_cidriving level": One pin can output 3.0v or 1.8v, depending on the
108c2ecf20Sopenharmony_cirelated domain pad driving selection, if the related domain pad
118c2ecf20Sopenharmony_cislect 3.0v, then the pin can output 3.0v. "system control" is used
128c2ecf20Sopenharmony_cito choose one function (like: UART0) for which system, since we
138c2ecf20Sopenharmony_cihave several systems (AP/CP/CM4) on one SoC.).
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158c2ecf20Sopenharmony_ciThere are too much various configuration that we can not list all
168c2ecf20Sopenharmony_ciof them, so we can not make every Spreadtrum-special configuration
178c2ecf20Sopenharmony_cias one generic configuration, and maybe it will add more strange
188c2ecf20Sopenharmony_ciglobal configuration in future. Then we add one "sprd,control" to
198c2ecf20Sopenharmony_ciset these various global control configuration, and we need use
208c2ecf20Sopenharmony_cimagic number for this property.
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228c2ecf20Sopenharmony_ciMoreover we recognise every fields comprising one bit or several
238c2ecf20Sopenharmony_cibits in one global control register as one pin, thus we should
248c2ecf20Sopenharmony_cirecord every pin's bit offset, bit width and register offset to
258c2ecf20Sopenharmony_ciconfigure this field (pin).
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278c2ecf20Sopenharmony_ciThe second block comprises some common registers which have unified
288c2ecf20Sopenharmony_ciregister definition, and each register described one pin is used
298c2ecf20Sopenharmony_cito configure the pin sleep mode, function select and sleep related
308c2ecf20Sopenharmony_ciconfiguration.
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328c2ecf20Sopenharmony_ciNow we have 4 systems for sleep mode on SC9860 SoC: AP system,
338c2ecf20Sopenharmony_ciPUBCP system, TGLDSP system and AGDSP system. And the pin sleep
348c2ecf20Sopenharmony_cirelated configuration are:
358c2ecf20Sopenharmony_ci- input-enable
368c2ecf20Sopenharmony_ci- input-disable
378c2ecf20Sopenharmony_ci- output-high
388c2ecf20Sopenharmony_ci- output-low
398c2ecf20Sopenharmony_ci- bias-pull-up
408c2ecf20Sopenharmony_ci- bias-pull-down
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428c2ecf20Sopenharmony_ciIn some situation we need set the pin sleep mode and pin sleep related
438c2ecf20Sopenharmony_ciconfiguration, to set the pin sleep related configuration automatically
448c2ecf20Sopenharmony_ciby hardware when the system specified by sleep mode goes into deep
458c2ecf20Sopenharmony_cisleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP
468c2ecf20Sopenharmony_ciand set the pin sleep related configuration as "input-enable", which
478c2ecf20Sopenharmony_cimeans when PUBCP system goes into deep sleep mode, this pin will be set
488c2ecf20Sopenharmony_ciinput enable automatically.
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508c2ecf20Sopenharmony_ciMoreover we can not use the "sleep" state, since some systems (like:
518c2ecf20Sopenharmony_ciPUBCP system) do not run linux kernel OS (only AP system run linux
528c2ecf20Sopenharmony_cikernel on SC9860 platform), then we can not select "sleep" state
538c2ecf20Sopenharmony_ciwhen the PUBCP system goes into deep sleep mode. Thus we introduce
548c2ecf20Sopenharmony_ci"sprd,sleep-mode" property to set pin sleep mode.
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568c2ecf20Sopenharmony_ciThe last block comprises some misc registers which also have unified
578c2ecf20Sopenharmony_ciregister definition, and each register described one pin is used to
588c2ecf20Sopenharmony_ciconfigure drive strength, pull up/down and so on. Especially for pull
598c2ecf20Sopenharmony_ciup, we have two kind pull up resistor: 20K and 4.7K.
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618c2ecf20Sopenharmony_ciRequired properties for Spreadtrum pin controller:
628c2ecf20Sopenharmony_ci- compatible: "sprd,<soc>-pinctrl"
638c2ecf20Sopenharmony_ci  Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported SoCs.
648c2ecf20Sopenharmony_ci- reg: The register address of pin controller device.
658c2ecf20Sopenharmony_ci- pins : An array of pin names.
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678c2ecf20Sopenharmony_ciOptional properties:
688c2ecf20Sopenharmony_ci- function: Specified the function name.
698c2ecf20Sopenharmony_ci- drive-strength: Drive strength in mA.
708c2ecf20Sopenharmony_ci- input-schmitt-disable: Enable schmitt-trigger mode.
718c2ecf20Sopenharmony_ci- input-schmitt-enable: Disable schmitt-trigger mode.
728c2ecf20Sopenharmony_ci- bias-disable: Disable pin bias.
738c2ecf20Sopenharmony_ci- bias-pull-down: Pull down on pin.
748c2ecf20Sopenharmony_ci- bias-pull-up: Pull up on pin.
758c2ecf20Sopenharmony_ci- input-enable: Enable pin input.
768c2ecf20Sopenharmony_ci- input-disable: Enable pin output.
778c2ecf20Sopenharmony_ci- output-high: Set the pin as an output level high.
788c2ecf20Sopenharmony_ci- output-low: Set the pin as an output level low.
798c2ecf20Sopenharmony_ci- sleep-hardware-state: Indicate these configs in this state are sleep related.
808c2ecf20Sopenharmony_ci- sprd,control: Control values referring to databook for global control pins.
818c2ecf20Sopenharmony_ci- sprd,sleep-mode: Sleep mode selection.
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838c2ecf20Sopenharmony_ciPlease refer to each sprd,<soc>-pinctrl.txt binding doc for supported values.
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