18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 28c2ecf20Sopenharmony_ci%YAML 1.2 38c2ecf20Sopenharmony_ci--- 48c2ecf20Sopenharmony_ci$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml# 58c2ecf20Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_cititle: Renesas RZ/A1 combined Pin and GPIO controller 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_cimaintainers: 108c2ecf20Sopenharmony_ci - Jacopo Mondi <jacopo+renesas@jmondi.org> 118c2ecf20Sopenharmony_ci - Geert Uytterhoeven <geert+renesas@glider.be> 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_cidescription: 148c2ecf20Sopenharmony_ci The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO 158c2ecf20Sopenharmony_ci controller, named "Ports" in the hardware reference manual. 168c2ecf20Sopenharmony_ci Pin multiplexing and GPIO configuration is performed on a per-pin basis 178c2ecf20Sopenharmony_ci writing configuration values to per-port register sets. 188c2ecf20Sopenharmony_ci Each "port" features up to 16 pins, each of them configurable for GPIO 198c2ecf20Sopenharmony_ci function (port mode) or in alternate function mode. 208c2ecf20Sopenharmony_ci Up to 8 different alternate function modes exist for each single pin. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ciproperties: 238c2ecf20Sopenharmony_ci compatible: 248c2ecf20Sopenharmony_ci oneOf: 258c2ecf20Sopenharmony_ci - const: renesas,r7s72100-ports # RZ/A1H 268c2ecf20Sopenharmony_ci - items: 278c2ecf20Sopenharmony_ci - const: renesas,r7s72101-ports # RZ/A1M 288c2ecf20Sopenharmony_ci - const: renesas,r7s72100-ports # fallback 298c2ecf20Sopenharmony_ci - const: renesas,r7s72102-ports # RZ/A1L 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci reg: 328c2ecf20Sopenharmony_ci maxItems: 1 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_cirequired: 358c2ecf20Sopenharmony_ci - compatible 368c2ecf20Sopenharmony_ci - reg 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_cipatternProperties: 398c2ecf20Sopenharmony_ci "^gpio-[0-9]*$": 408c2ecf20Sopenharmony_ci type: object 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci description: 438c2ecf20Sopenharmony_ci Each port of the r7s72100 pin controller hardware is itself a GPIO 448c2ecf20Sopenharmony_ci controller. 458c2ecf20Sopenharmony_ci Different SoCs have different numbers of available pins per port, but 468c2ecf20Sopenharmony_ci generally speaking, each of them can be configured in GPIO ("port") mode 478c2ecf20Sopenharmony_ci on this hardware. 488c2ecf20Sopenharmony_ci Describe GPIO controllers using sub-nodes with the following properties. 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci properties: 518c2ecf20Sopenharmony_ci gpio-controller: true 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ci '#gpio-cells': 548c2ecf20Sopenharmony_ci const: 2 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci gpio-ranges: 578c2ecf20Sopenharmony_ci maxItems: 1 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ci required: 608c2ecf20Sopenharmony_ci - gpio-controller 618c2ecf20Sopenharmony_ci - '#gpio-cells' 628c2ecf20Sopenharmony_ci - gpio-ranges 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_ci 658c2ecf20Sopenharmony_ciadditionalProperties: 668c2ecf20Sopenharmony_ci anyOf: 678c2ecf20Sopenharmony_ci - type: object 688c2ecf20Sopenharmony_ci allOf: 698c2ecf20Sopenharmony_ci - $ref: pincfg-node.yaml# 708c2ecf20Sopenharmony_ci - $ref: pinmux-node.yaml# 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci description: 738c2ecf20Sopenharmony_ci A pin multiplexing sub-node describes how to configure a set of (or a 748c2ecf20Sopenharmony_ci single) pin in some desired alternate function mode. 758c2ecf20Sopenharmony_ci A single sub-node may define several pin configurations. 768c2ecf20Sopenharmony_ci A few alternate function require special pin configuration flags to be 778c2ecf20Sopenharmony_ci supplied along with the alternate function configuration number. 788c2ecf20Sopenharmony_ci The hardware reference manual specifies when a pin function requires 798c2ecf20Sopenharmony_ci "software IO driven" mode to be specified. To do so use the generic 808c2ecf20Sopenharmony_ci properties from the <include/linux/pinctrl/pinconf_generic.h> header 818c2ecf20Sopenharmony_ci file to instruct the pin controller to perform the desired pin 828c2ecf20Sopenharmony_ci configuration operation. 838c2ecf20Sopenharmony_ci The hardware reference manual specifies when a pin has to be configured 848c2ecf20Sopenharmony_ci to work in bi-directional mode and when the IO direction has to be 858c2ecf20Sopenharmony_ci specified by software. Bi-directional pins must be managed by the pin 868c2ecf20Sopenharmony_ci controller driver internally, while software driven IO direction has to 878c2ecf20Sopenharmony_ci be explicitly selected when multiple options are available. 888c2ecf20Sopenharmony_ci 898c2ecf20Sopenharmony_ci properties: 908c2ecf20Sopenharmony_ci pinmux: 918c2ecf20Sopenharmony_ci description: | 928c2ecf20Sopenharmony_ci Integer array representing pin number and pin multiplexing 938c2ecf20Sopenharmony_ci configuration. 948c2ecf20Sopenharmony_ci When a pin has to be configured in alternate function mode, use 958c2ecf20Sopenharmony_ci this property to identify the pin by its global index, and provide 968c2ecf20Sopenharmony_ci its alternate function configuration number along with it. 978c2ecf20Sopenharmony_ci When multiple pins are required to be configured as part of the 988c2ecf20Sopenharmony_ci same alternate function they shall be specified as members of the 998c2ecf20Sopenharmony_ci same argument list of a single "pinmux" property. 1008c2ecf20Sopenharmony_ci Helper macros to ease assembling the pin index from its position 1018c2ecf20Sopenharmony_ci (port where it sits on and pin number) and alternate function 1028c2ecf20Sopenharmony_ci identifier are provided by the pin controller header file at: 1038c2ecf20Sopenharmony_ci <include/dt-bindings/pinctrl/r7s72100-pinctrl.h> 1048c2ecf20Sopenharmony_ci Integers values in "pinmux" argument list are assembled as: 1058c2ecf20Sopenharmony_ci ((PORT * 16 + PIN) | MUX_FUNC << 16) 1068c2ecf20Sopenharmony_ci 1078c2ecf20Sopenharmony_ci phandle: true 1088c2ecf20Sopenharmony_ci input-enable: true 1098c2ecf20Sopenharmony_ci output-enable: true 1108c2ecf20Sopenharmony_ci 1118c2ecf20Sopenharmony_ci required: 1128c2ecf20Sopenharmony_ci - pinmux 1138c2ecf20Sopenharmony_ci 1148c2ecf20Sopenharmony_ci additionalProperties: false 1158c2ecf20Sopenharmony_ci 1168c2ecf20Sopenharmony_ci - type: object 1178c2ecf20Sopenharmony_ci properties: 1188c2ecf20Sopenharmony_ci phandle: true 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_ci additionalProperties: 1218c2ecf20Sopenharmony_ci $ref: "#/additionalProperties/anyOf/0" 1228c2ecf20Sopenharmony_ci 1238c2ecf20Sopenharmony_ciexamples: 1248c2ecf20Sopenharmony_ci - | 1258c2ecf20Sopenharmony_ci #include <dt-bindings/pinctrl/r7s72100-pinctrl.h> 1268c2ecf20Sopenharmony_ci pinctrl: pinctrl@fcfe3000 { 1278c2ecf20Sopenharmony_ci compatible = "renesas,r7s72100-ports"; 1288c2ecf20Sopenharmony_ci 1298c2ecf20Sopenharmony_ci reg = <0xfcfe3000 0x4230>; 1308c2ecf20Sopenharmony_ci 1318c2ecf20Sopenharmony_ci /* 1328c2ecf20Sopenharmony_ci * A GPIO controller node, controlling 16 pins indexed from 0. 1338c2ecf20Sopenharmony_ci * The GPIO controller base in the global pin indexing space is pin 1348c2ecf20Sopenharmony_ci * 48, thus pins [0 - 15] on this controller map to pins [48 - 63] 1358c2ecf20Sopenharmony_ci * in the global pin indexing space. 1368c2ecf20Sopenharmony_ci */ 1378c2ecf20Sopenharmony_ci port3: gpio-3 { 1388c2ecf20Sopenharmony_ci gpio-controller; 1398c2ecf20Sopenharmony_ci #gpio-cells = <2>; 1408c2ecf20Sopenharmony_ci gpio-ranges = <&pinctrl 0 48 16>; 1418c2ecf20Sopenharmony_ci }; 1428c2ecf20Sopenharmony_ci 1438c2ecf20Sopenharmony_ci /* 1448c2ecf20Sopenharmony_ci * A serial communication interface with a TX output pin and an RX 1458c2ecf20Sopenharmony_ci * input pin. 1468c2ecf20Sopenharmony_ci * Pin #0 on port #3 is configured as alternate function #6. 1478c2ecf20Sopenharmony_ci * Pin #2 on port #3 is configured as alternate function #4. 1488c2ecf20Sopenharmony_ci */ 1498c2ecf20Sopenharmony_ci scif2_pins: serial2 { 1508c2ecf20Sopenharmony_ci pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>; 1518c2ecf20Sopenharmony_ci }; 1528c2ecf20Sopenharmony_ci 1538c2ecf20Sopenharmony_ci 1548c2ecf20Sopenharmony_ci /* 1558c2ecf20Sopenharmony_ci * I2c master: both SDA and SCL pins need bi-directional operations 1568c2ecf20Sopenharmony_ci * Pin #4 on port #1 is configured as alternate function #1. 1578c2ecf20Sopenharmony_ci * Pin #5 on port #1 is configured as alternate function #1. 1588c2ecf20Sopenharmony_ci * Both need to work in bi-directional mode, the driver must manage 1598c2ecf20Sopenharmony_ci * this internally. 1608c2ecf20Sopenharmony_ci */ 1618c2ecf20Sopenharmony_ci i2c2_pins: i2c2 { 1628c2ecf20Sopenharmony_ci pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>; 1638c2ecf20Sopenharmony_ci }; 1648c2ecf20Sopenharmony_ci 1658c2ecf20Sopenharmony_ci 1668c2ecf20Sopenharmony_ci /* 1678c2ecf20Sopenharmony_ci * Multi-function timer input and output compare pins. 1688c2ecf20Sopenharmony_ci */ 1698c2ecf20Sopenharmony_ci tioc0_pins: tioc0 { 1708c2ecf20Sopenharmony_ci /* 1718c2ecf20Sopenharmony_ci * Configure TIOC0A as software driven input 1728c2ecf20Sopenharmony_ci * Pin #0 on port #4 is configured as alternate function #2 1738c2ecf20Sopenharmony_ci * with IO direction specified by software as input. 1748c2ecf20Sopenharmony_ci */ 1758c2ecf20Sopenharmony_ci tioc0_input_pins { 1768c2ecf20Sopenharmony_ci pinmux = <RZA1_PINMUX(4, 0, 2)>; 1778c2ecf20Sopenharmony_ci input-enable; 1788c2ecf20Sopenharmony_ci }; 1798c2ecf20Sopenharmony_ci 1808c2ecf20Sopenharmony_ci /* 1818c2ecf20Sopenharmony_ci * Configure TIOC0B as software driven output 1828c2ecf20Sopenharmony_ci * Pin #1 on port #4 is configured as alternate function #1 1838c2ecf20Sopenharmony_ci * with IO direction specified by software as output. 1848c2ecf20Sopenharmony_ci */ 1858c2ecf20Sopenharmony_ci tioc0_output_pins { 1868c2ecf20Sopenharmony_ci pinmux = <RZA1_PINMUX(4, 1, 1)>; 1878c2ecf20Sopenharmony_ci output-enable; 1888c2ecf20Sopenharmony_ci }; 1898c2ecf20Sopenharmony_ci }; 1908c2ecf20Sopenharmony_ci }; 191