18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only
28c2ecf20Sopenharmony_ci%YAML 1.2
38c2ecf20Sopenharmony_ci---
48c2ecf20Sopenharmony_ci$id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
58c2ecf20Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_cititle: Generic pin multiplexing node schema
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_cimaintainers:
108c2ecf20Sopenharmony_ci  - Linus Walleij <linus.walleij@linaro.org>
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_cidescription: |
138c2ecf20Sopenharmony_ci  The contents of the pin configuration child nodes are defined by the binding
148c2ecf20Sopenharmony_ci  for the individual pin controller device. The pin configuration nodes need not
158c2ecf20Sopenharmony_ci  be direct children of the pin controller device; they may be grandchildren,
168c2ecf20Sopenharmony_ci  for example. Whether this is legal, and whether there is any interaction
178c2ecf20Sopenharmony_ci  between the child and intermediate parent nodes, is again defined entirely by
188c2ecf20Sopenharmony_ci  the binding for the individual pin controller device.
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ci  While not required to be used, there are 3 generic forms of pin muxing nodes
218c2ecf20Sopenharmony_ci  which pin controller devices can use.
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci  pin multiplexing nodes:
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_ci  Example:
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ci  state_0_node_a {
288c2ecf20Sopenharmony_ci    uart0 {
298c2ecf20Sopenharmony_ci      function = "uart0";
308c2ecf20Sopenharmony_ci      groups = "u0rxtx", "u0rtscts";
318c2ecf20Sopenharmony_ci    };
328c2ecf20Sopenharmony_ci  };
338c2ecf20Sopenharmony_ci  state_1_node_a {
348c2ecf20Sopenharmony_ci    spi0 {
358c2ecf20Sopenharmony_ci      function = "spi0";
368c2ecf20Sopenharmony_ci      groups = "spi0pins";
378c2ecf20Sopenharmony_ci    };
388c2ecf20Sopenharmony_ci  };
398c2ecf20Sopenharmony_ci  state_2_node_a {
408c2ecf20Sopenharmony_ci    function = "i2c0";
418c2ecf20Sopenharmony_ci    pins = "mfio29", "mfio30";
428c2ecf20Sopenharmony_ci  };
438c2ecf20Sopenharmony_ci
448c2ecf20Sopenharmony_ci  Optionally an alternative binding can be used if more suitable depending on the
458c2ecf20Sopenharmony_ci  pin controller hardware. For hardware where there is a large number of identical
468c2ecf20Sopenharmony_ci  pin controller instances, naming each pin and function can easily become
478c2ecf20Sopenharmony_ci  unmaintainable. This is especially the case if the same controller is used for
488c2ecf20Sopenharmony_ci  different pins and functions depending on the SoC revision and packaging.
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_ci  For cases like this, the pin controller driver may use pinctrl-pin-array helper
518c2ecf20Sopenharmony_ci  binding with a hardware based index and a number of pin configuration values:
528c2ecf20Sopenharmony_ci
538c2ecf20Sopenharmony_ci  pincontroller {
548c2ecf20Sopenharmony_ci    ... /* Standard DT properties for the device itself elided */
558c2ecf20Sopenharmony_ci    #pinctrl-cells = <2>;
568c2ecf20Sopenharmony_ci
578c2ecf20Sopenharmony_ci    state_0_node_a {
588c2ecf20Sopenharmony_ci      pinctrl-pin-array = <
598c2ecf20Sopenharmony_ci        0 A_DELAY_PS(0) G_DELAY_PS(120)
608c2ecf20Sopenharmony_ci        4 A_DELAY_PS(0) G_DELAY_PS(360)
618c2ecf20Sopenharmony_ci        ...
628c2ecf20Sopenharmony_ci        >;
638c2ecf20Sopenharmony_ci    };
648c2ecf20Sopenharmony_ci    ...
658c2ecf20Sopenharmony_ci  };
668c2ecf20Sopenharmony_ci
678c2ecf20Sopenharmony_ci  Above #pinctrl-cells specifies the number of value cells in addition to the
688c2ecf20Sopenharmony_ci  index of the registers. This is similar to the interrupts-extended binding with
698c2ecf20Sopenharmony_ci  one exception. There is no need to specify the phandle for each entry as that
708c2ecf20Sopenharmony_ci  is already known as the defined pins are always children of the pin controller
718c2ecf20Sopenharmony_ci  node. Further having the phandle pointing to another pin controller would not
728c2ecf20Sopenharmony_ci  currently work as the pinctrl framework uses named modes to group pins for each
738c2ecf20Sopenharmony_ci  pin control device.
748c2ecf20Sopenharmony_ci
758c2ecf20Sopenharmony_ci  The index for pinctrl-pin-array must relate to the hardware for the pinctrl
768c2ecf20Sopenharmony_ci  registers, and must not be a virtual index of pin instances. The reason for
778c2ecf20Sopenharmony_ci  this is to avoid mapping of the index in the dts files and the pin controller
788c2ecf20Sopenharmony_ci  driver as it can change.
798c2ecf20Sopenharmony_ci
808c2ecf20Sopenharmony_ci  For hardware where pin multiplexing configurations have to be specified for
818c2ecf20Sopenharmony_ci  each single pin the number of required sub-nodes containing "pin" and
828c2ecf20Sopenharmony_ci  "function" properties can quickly escalate and become hard to write and
838c2ecf20Sopenharmony_ci  maintain.
848c2ecf20Sopenharmony_ci
858c2ecf20Sopenharmony_ci  For cases like this, the pin controller driver may use the pinmux helper
868c2ecf20Sopenharmony_ci  property, where the pin identifier is provided with mux configuration settings
878c2ecf20Sopenharmony_ci  in a pinmux group. A pinmux group consists of the pin identifier and mux
888c2ecf20Sopenharmony_ci  settings represented as a single integer or an array of integers.
898c2ecf20Sopenharmony_ci
908c2ecf20Sopenharmony_ci  The pinmux property accepts an array of pinmux groups, each of them describing
918c2ecf20Sopenharmony_ci  a single pin multiplexing configuration.
928c2ecf20Sopenharmony_ci
938c2ecf20Sopenharmony_ci  pincontroller {
948c2ecf20Sopenharmony_ci    state_0_node_a {
958c2ecf20Sopenharmony_ci      pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
968c2ecf20Sopenharmony_ci    };
978c2ecf20Sopenharmony_ci  };
988c2ecf20Sopenharmony_ci
998c2ecf20Sopenharmony_ci  Each individual pin controller driver bindings documentation shall specify
1008c2ecf20Sopenharmony_ci  how pin IDs and pin multiplexing configuration are defined and assembled
1018c2ecf20Sopenharmony_ci  together in a pinmux group.
1028c2ecf20Sopenharmony_ci
1038c2ecf20Sopenharmony_ciproperties:
1048c2ecf20Sopenharmony_ci  function:
1058c2ecf20Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/string
1068c2ecf20Sopenharmony_ci    description: The mux function to select
1078c2ecf20Sopenharmony_ci
1088c2ecf20Sopenharmony_ci  pins:
1098c2ecf20Sopenharmony_ci    oneOf:
1108c2ecf20Sopenharmony_ci      - $ref: /schemas/types.yaml#/definitions/uint32-array
1118c2ecf20Sopenharmony_ci      - $ref: /schemas/types.yaml#/definitions/string-array
1128c2ecf20Sopenharmony_ci    description:
1138c2ecf20Sopenharmony_ci      The list of pin identifiers that properties in the node apply to. The
1148c2ecf20Sopenharmony_ci      specific binding for the hardware defines whether the entries are integers
1158c2ecf20Sopenharmony_ci      or strings, and their meaning.
1168c2ecf20Sopenharmony_ci
1178c2ecf20Sopenharmony_ci  groups:
1188c2ecf20Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/string-array
1198c2ecf20Sopenharmony_ci    description:
1208c2ecf20Sopenharmony_ci      the group to apply the properties to, if the driver supports
1218c2ecf20Sopenharmony_ci      configuration of whole groups rather than individual pins (either
1228c2ecf20Sopenharmony_ci      this, "pins" or "pinmux" has to be specified)
1238c2ecf20Sopenharmony_ci
1248c2ecf20Sopenharmony_ci  pinmux:
1258c2ecf20Sopenharmony_ci    description:
1268c2ecf20Sopenharmony_ci      The list of numeric pin ids and their mux settings that properties in the
1278c2ecf20Sopenharmony_ci      node apply to (either this, "pins" or "groups" have to be specified)
1288c2ecf20Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/uint32-array
1298c2ecf20Sopenharmony_ci
1308c2ecf20Sopenharmony_ci  pinctrl-pin-array:
1318c2ecf20Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/uint32-array
1328c2ecf20Sopenharmony_ci
1338c2ecf20Sopenharmony_ciadditionalProperties: true
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