18c2ecf20Sopenharmony_ci* MediaTek MT6797 Pin Controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThe MediaTek's MT6797 Pin controller is used to control SoC pins.
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ciRequired properties:
68c2ecf20Sopenharmony_ci- compatible: Value should be one of the following.
78c2ecf20Sopenharmony_ci              "mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl.
88c2ecf20Sopenharmony_ci- reg:        Should contain address and size for gpio, iocfgl, iocfgb,
98c2ecf20Sopenharmony_ci              iocfgr and iocfgt register bases.
108c2ecf20Sopenharmony_ci- reg-names:  An array of strings describing the "reg" entries. Must
118c2ecf20Sopenharmony_ci              contain "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt".
128c2ecf20Sopenharmony_ci- gpio-controller: Marks the device node as a gpio controller.
138c2ecf20Sopenharmony_ci- #gpio-cells: Should be two. The first cell is the gpio pin number
148c2ecf20Sopenharmony_ci               and the second cell is used for optional parameters.
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ciOptional properties:
178c2ecf20Sopenharmony_ci- interrupt-controller: Marks the device node as an interrupt controller.
188c2ecf20Sopenharmony_ci- #interrupt-cells: Should be two.
198c2ecf20Sopenharmony_ci- interrupts : The interrupt outputs from the controller.
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ciPlease refer to pinctrl-bindings.txt in this directory for details of the
228c2ecf20Sopenharmony_cicommon pinctrl bindings used by client devices.
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ciSubnode format
258c2ecf20Sopenharmony_ciA pinctrl node should contain at least one subnodes representing the
268c2ecf20Sopenharmony_cipinctrl groups available on the machine. Each subnode will list the
278c2ecf20Sopenharmony_cipins it needs, and how they should be configured, with regard to muxer
288c2ecf20Sopenharmony_ciconfiguration, pullups, drive strength, input enable/disable and input schmitt.
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci    node {
318c2ecf20Sopenharmony_ci        pinmux = <PIN_NUMBER_PINMUX>;
328c2ecf20Sopenharmony_ci        GENERIC_PINCONFIG;
338c2ecf20Sopenharmony_ci    };
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ciRequired properties:
368c2ecf20Sopenharmony_ci- pinmux: Integer array, represents gpio pin number and mux setting.
378c2ecf20Sopenharmony_ci    Supported pin number and mux varies for different SoCs, and are defined
388c2ecf20Sopenharmony_ci    as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ciOptional properties:
418c2ecf20Sopenharmony_ci- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
428c2ecf20Sopenharmony_ci    bias-pull, bias-pull-down, input-enable, input-schmitt-enable,
438c2ecf20Sopenharmony_ci    input-schmitt-disable, output-enable output-low, output-high,
448c2ecf20Sopenharmony_ci    drive-strength, and slew-rate are valid.
458c2ecf20Sopenharmony_ci
468c2ecf20Sopenharmony_ci    Valid arguments for 'slew-rate' are '0' for no slew rate controlled and
478c2ecf20Sopenharmony_ci    '1' for slower slew rate respectively. Valid arguments for 'drive-strength'
488c2ecf20Sopenharmony_ci    is limited, such as 2, 4, 8, 12, or 16 in mA.
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_ci    Some optional vendor properties as defined are valid to specify in a
518c2ecf20Sopenharmony_ci    pinconf subnode:
528c2ecf20Sopenharmony_ci    - mediatek,tdsel: An integer describing the steps for output level shifter
538c2ecf20Sopenharmony_ci      duty cycle when asserted (high pulse width adjustment). Valid arguments
548c2ecf20Sopenharmony_ci      are from 0 to 15.
558c2ecf20Sopenharmony_ci    - mediatek,rdsel: An integer describing the steps for input level shifter
568c2ecf20Sopenharmony_ci      duty cycle when asserted (high pulse width adjustment). Valid arguments
578c2ecf20Sopenharmony_ci      are from 0 to 63.
588c2ecf20Sopenharmony_ci    - mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2
598c2ecf20Sopenharmony_ci      or 3 for the advanced pull-up resistors.
608c2ecf20Sopenharmony_ci    - mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2,
618c2ecf20Sopenharmony_ci      or 3 for the advanced pull-down resistors.
628c2ecf20Sopenharmony_ci
638c2ecf20Sopenharmony_ciExamples:
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_ci        pio: pinctrl@10005000 {
668c2ecf20Sopenharmony_ci                compatible = "mediatek,mt6797-pinctrl";
678c2ecf20Sopenharmony_ci                reg = <0 0x10005000 0 0x1000>,
688c2ecf20Sopenharmony_ci                      <0 0x10002000 0 0x400>,
698c2ecf20Sopenharmony_ci                      <0 0x10002400 0 0x400>,
708c2ecf20Sopenharmony_ci                      <0 0x10002800 0 0x400>,
718c2ecf20Sopenharmony_ci                      <0 0x10002C00 0 0x400>;
728c2ecf20Sopenharmony_ci                reg-names = "gpio", "iocfgl", "iocfgb",
738c2ecf20Sopenharmony_ci                            "iocfgr", "iocfgt";
748c2ecf20Sopenharmony_ci                gpio-controller;
758c2ecf20Sopenharmony_ci                #gpio-cells = <2>;
768c2ecf20Sopenharmony_ci
778c2ecf20Sopenharmony_ci                uart1_pins_a: uart1 {
788c2ecf20Sopenharmony_ci                        pins1 {
798c2ecf20Sopenharmony_ci                                pinmux = <MT6797_GPIO232__FUNC_URXD1>,
808c2ecf20Sopenharmony_ci                                         <MT6797_GPIO233__FUNC_UTXD1>;
818c2ecf20Sopenharmony_ci                        };
828c2ecf20Sopenharmony_ci                };
838c2ecf20Sopenharmony_ci        };
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