18c2ecf20Sopenharmony_ciMicrochip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for 28c2ecf20Sopenharmony_ci8-/16-bit I/O expander with serial interface (I2C/SPI) 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciRequired properties: 58c2ecf20Sopenharmony_ci- compatible : Should be 68c2ecf20Sopenharmony_ci - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version 78c2ecf20Sopenharmony_ci - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version 88c2ecf20Sopenharmony_ci - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or 98c2ecf20Sopenharmony_ci - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci - "microchip,mcp23s08" for 8 GPIO SPI version 128c2ecf20Sopenharmony_ci - "microchip,mcp23s17" for 16 GPIO SPI version 138c2ecf20Sopenharmony_ci - "microchip,mcp23s18" for 16 GPIO SPI version 148c2ecf20Sopenharmony_ci - "microchip,mcp23008" for 8 GPIO I2C version or 158c2ecf20Sopenharmony_ci - "microchip,mcp23017" for 16 GPIO I2C version of the chip 168c2ecf20Sopenharmony_ci - "microchip,mcp23018" for 16 GPIO I2C version 178c2ecf20Sopenharmony_ci NOTE: Do not use the old mcp prefix any more. It is deprecated and will be 188c2ecf20Sopenharmony_ci removed. 198c2ecf20Sopenharmony_ci- #gpio-cells : Should be two. 208c2ecf20Sopenharmony_ci - first cell is the pin number 218c2ecf20Sopenharmony_ci - second cell is used to specify flags as described in 228c2ecf20Sopenharmony_ci 'Documentation/devicetree/bindings/gpio/gpio.txt'. Allowed values defined by 238c2ecf20Sopenharmony_ci 'include/dt-bindings/gpio/gpio.h' (e.g. GPIO_ACTIVE_LOW). 248c2ecf20Sopenharmony_ci- gpio-controller : Marks the device node as a GPIO controller. 258c2ecf20Sopenharmony_ci- reg : For an address on its bus. I2C uses this a the I2C address of the chip. 268c2ecf20Sopenharmony_ci SPI uses this to specify the chipselect line which the chip is 278c2ecf20Sopenharmony_ci connected to. The driver and the SPI variant of the chip support 288c2ecf20Sopenharmony_ci multiple chips on the same chipselect. Have a look at 298c2ecf20Sopenharmony_ci microchip,spi-present-mask below. 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ciRequired device specific properties (only for SPI chips): 328c2ecf20Sopenharmony_ci- mcp,spi-present-mask (DEPRECATED) 338c2ecf20Sopenharmony_ci- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI 348c2ecf20Sopenharmony_ci chips - as the name suggests. Multiple SPI chips can share the same 358c2ecf20Sopenharmony_ci SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a 368c2ecf20Sopenharmony_ci chip connected with the corresponding spi address set. For example if 378c2ecf20Sopenharmony_ci you have a chip with address 3 connected, you have to set bit3 to 1, 388c2ecf20Sopenharmony_ci which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not 398c2ecf20Sopenharmony_ci possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at 408c2ecf20Sopenharmony_ci least one bit to 1 for SPI chips. 418c2ecf20Sopenharmony_ci NOTE: Do not use the old mcp prefix any more. It is deprecated and will be 428c2ecf20Sopenharmony_ci removed. 438c2ecf20Sopenharmony_ci- spi-max-frequency = The maximum frequency this chip is able to handle 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_ciOptional properties: 468c2ecf20Sopenharmony_ci- #interrupt-cells : Should be two. 478c2ecf20Sopenharmony_ci - first cell is the pin number 488c2ecf20Sopenharmony_ci - second cell is used to specify flags. 498c2ecf20Sopenharmony_ci- interrupt-controller: Marks the device node as a interrupt controller. 508c2ecf20Sopenharmony_ci- drive-open-drain: Sets the ODR flag in the IOCON register. This configures 518c2ecf20Sopenharmony_ci the IRQ output as open drain active low. 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ciOptional device specific properties: 548c2ecf20Sopenharmony_ci- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices 558c2ecf20Sopenharmony_ci with two interrupt outputs (these are the devices ending with 17 and 568c2ecf20Sopenharmony_ci those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and 578c2ecf20Sopenharmony_ci IO 8-15 are bank 2. These chips have two different interrupt outputs: 588c2ecf20Sopenharmony_ci One for bank 1 and another for bank 2. If irq-mirror is set, both 598c2ecf20Sopenharmony_ci interrupts are generated regardless of the bank that an input change 608c2ecf20Sopenharmony_ci occurred on. If it is not set, the interrupt are only generated for the 618c2ecf20Sopenharmony_ci bank they belong to. 628c2ecf20Sopenharmony_ci On devices with only one interrupt output this property is useless. 638c2ecf20Sopenharmony_ci- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This 648c2ecf20Sopenharmony_ci configures the IRQ output polarity as active high. 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ciExample I2C (with interrupt): 678c2ecf20Sopenharmony_cigpiom1: gpio@20 { 688c2ecf20Sopenharmony_ci compatible = "microchip,mcp23017"; 698c2ecf20Sopenharmony_ci gpio-controller; 708c2ecf20Sopenharmony_ci #gpio-cells = <2>; 718c2ecf20Sopenharmony_ci reg = <0x20>; 728c2ecf20Sopenharmony_ci 738c2ecf20Sopenharmony_ci interrupt-parent = <&gpio1>; 748c2ecf20Sopenharmony_ci interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 758c2ecf20Sopenharmony_ci interrupt-controller; 768c2ecf20Sopenharmony_ci #interrupt-cells=<2>; 778c2ecf20Sopenharmony_ci microchip,irq-mirror; 788c2ecf20Sopenharmony_ci}; 798c2ecf20Sopenharmony_ci 808c2ecf20Sopenharmony_ciExample SPI: 818c2ecf20Sopenharmony_cigpiom1: gpio@0 { 828c2ecf20Sopenharmony_ci compatible = "microchip,mcp23s17"; 838c2ecf20Sopenharmony_ci gpio-controller; 848c2ecf20Sopenharmony_ci #gpio-cells = <2>; 858c2ecf20Sopenharmony_ci microchip,spi-present-mask = <0x01>; 868c2ecf20Sopenharmony_ci reg = <0>; 878c2ecf20Sopenharmony_ci spi-max-frequency = <1000000>; 888c2ecf20Sopenharmony_ci}; 898c2ecf20Sopenharmony_ci 908c2ecf20Sopenharmony_ciPull-up configuration 918c2ecf20Sopenharmony_ci===================== 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_ciIf pins are used as output, they can also be configured with pull-ups. This is 948c2ecf20Sopenharmony_cidone with pinctrl. 958c2ecf20Sopenharmony_ci 968c2ecf20Sopenharmony_ciPlease refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt> 978c2ecf20Sopenharmony_cifor details of the common pinctrl bindings used by client devices, 988c2ecf20Sopenharmony_ciincluding the meaning of the phrase "pin configuration node". 998c2ecf20Sopenharmony_ci 1008c2ecf20Sopenharmony_ciOptional Pinmux properties: 1018c2ecf20Sopenharmony_ci-------------------------- 1028c2ecf20Sopenharmony_ciFollowing properties are required if default setting of pins are required 1038c2ecf20Sopenharmony_ciat boot. 1048c2ecf20Sopenharmony_ci- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>. 1058c2ecf20Sopenharmony_ci- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per 1068c2ecf20Sopenharmony_ci <pinctrl-bindings.txt>. 1078c2ecf20Sopenharmony_ci 1088c2ecf20Sopenharmony_ciThe pin configurations are defined as child of the pinctrl states node. Each 1098c2ecf20Sopenharmony_cisub-node have following properties: 1108c2ecf20Sopenharmony_ci 1118c2ecf20Sopenharmony_ciRequired properties: 1128c2ecf20Sopenharmony_ci------------------ 1138c2ecf20Sopenharmony_ci- pins: List of pins. Valid values of pins properties are: 1148c2ecf20Sopenharmony_ci gpio0 ... gpio7 for the devices with 8 GPIO pins and 1158c2ecf20Sopenharmony_ci gpio0 ... gpio15 for the devices with 16 GPIO pins. 1168c2ecf20Sopenharmony_ci 1178c2ecf20Sopenharmony_ciOptional properties: 1188c2ecf20Sopenharmony_ci------------------- 1198c2ecf20Sopenharmony_ciThe following optional property is defined in the pinmux DT binding document 1208c2ecf20Sopenharmony_ci<pinctrl-bindings.txt>. Absence of this property will leave the configuration 1218c2ecf20Sopenharmony_ciin its default state. 1228c2ecf20Sopenharmony_ci bias-pull-up 1238c2ecf20Sopenharmony_ci 1248c2ecf20Sopenharmony_ciExample with pinctrl to pull-up output pins: 1258c2ecf20Sopenharmony_cigpio21: gpio@21 { 1268c2ecf20Sopenharmony_ci compatible = "microchip,mcp23017"; 1278c2ecf20Sopenharmony_ci gpio-controller; 1288c2ecf20Sopenharmony_ci #gpio-cells = <0x2>; 1298c2ecf20Sopenharmony_ci reg = <0x21>; 1308c2ecf20Sopenharmony_ci interrupt-parent = <&socgpio>; 1318c2ecf20Sopenharmony_ci interrupts = <0x17 0x8>; 1328c2ecf20Sopenharmony_ci interrupt-names = "mcp23017@21 irq"; 1338c2ecf20Sopenharmony_ci interrupt-controller; 1348c2ecf20Sopenharmony_ci #interrupt-cells = <0x2>; 1358c2ecf20Sopenharmony_ci microchip,irq-mirror; 1368c2ecf20Sopenharmony_ci pinctrl-names = "default"; 1378c2ecf20Sopenharmony_ci pinctrl-0 = <&i2cgpio0irq &gpio21pullups>; 1388c2ecf20Sopenharmony_ci 1398c2ecf20Sopenharmony_ci gpio21pullups: pinmux { 1408c2ecf20Sopenharmony_ci pins = "gpio0", "gpio1", "gpio2", "gpio3", 1418c2ecf20Sopenharmony_ci "gpio4", "gpio5", "gpio6", "gpio7", 1428c2ecf20Sopenharmony_ci "gpio8", "gpio9", "gpio10", "gpio11", 1438c2ecf20Sopenharmony_ci "gpio12", "gpio13", "gpio14", "gpio15"; 1448c2ecf20Sopenharmony_ci bias-pull-up; 1458c2ecf20Sopenharmony_ci }; 1468c2ecf20Sopenharmony_ci}; 147