18c2ecf20Sopenharmony_ciBroadcom iProc GPIO/PINCONF Controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci- compatible: 68c2ecf20Sopenharmony_ci "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that 78c2ecf20Sopenharmony_ci supports full-featured pinctrl and GPIO functions used in various iProc 88c2ecf20Sopenharmony_ci based SoCs 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci May contain an SoC-specific compatibility string to accommodate any 118c2ecf20Sopenharmony_ci SoC-specific features 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or 148c2ecf20Sopenharmony_ci "brcm,cygnus-crmu-gpio" for Cygnus SoCs 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support 178c2ecf20Sopenharmony_ci disabled 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general 208c2ecf20Sopenharmony_ci pinctrl support completely disabled in this IP block. In Stingray, a 218c2ecf20Sopenharmony_ci different IP block is used to handle pinctrl related functions 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci- reg: 248c2ecf20Sopenharmony_ci Define the base and range of the I/O address space that contains SoC 258c2ecf20Sopenharmony_ciGPIO/PINCONF controller registers 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci- ngpios: 288c2ecf20Sopenharmony_ci Total number of in-use slots in GPIO controller 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci- #gpio-cells: 318c2ecf20Sopenharmony_ci Must be two. The first cell is the GPIO pin number (within the 328c2ecf20Sopenharmony_cicontroller's pin space) and the second cell is used for the following: 338c2ecf20Sopenharmony_ci bit[0]: polarity (0 for active high and 1 for active low) 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci- gpio-controller: 368c2ecf20Sopenharmony_ci Specifies that the node is a GPIO controller 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ciOptional properties: 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ci- interrupts: 418c2ecf20Sopenharmony_ci Interrupt ID 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci- interrupt-controller: 448c2ecf20Sopenharmony_ci Specifies that the node is an interrupt controller 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci- gpio-ranges: 478c2ecf20Sopenharmony_ci Specifies the mapping between gpio controller and pin-controllers pins. 488c2ecf20Sopenharmony_ci This requires 4 fields in cells defined as - 498c2ecf20Sopenharmony_ci 1. Phandle of pin-controller. 508c2ecf20Sopenharmony_ci 2. GPIO base pin offset. 518c2ecf20Sopenharmony_ci 3 Pin-control base pin offset. 528c2ecf20Sopenharmony_ci 4. number of gpio pins which are linearly mapped from pin base. 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ciSupported generic PINCONF properties in child nodes: 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci- pins: 578c2ecf20Sopenharmony_ci The list of pins (within the controller's own pin space) that properties 588c2ecf20Sopenharmony_ciin the node apply to. Pin names are "gpio-<pin>" 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci- bias-disable: 618c2ecf20Sopenharmony_ci Disable pin bias 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci- bias-pull-up: 648c2ecf20Sopenharmony_ci Enable internal pull up resistor 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ci- bias-pull-down: 678c2ecf20Sopenharmony_ci Enable internal pull down resistor 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_ci- drive-strength: 708c2ecf20Sopenharmony_ci Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ciExample: 738c2ecf20Sopenharmony_ci gpio_ccm: gpio@1800a000 { 748c2ecf20Sopenharmony_ci compatible = "brcm,cygnus-ccm-gpio"; 758c2ecf20Sopenharmony_ci reg = <0x1800a000 0x50>, 768c2ecf20Sopenharmony_ci <0x0301d164 0x20>; 778c2ecf20Sopenharmony_ci ngpios = <24>; 788c2ecf20Sopenharmony_ci #gpio-cells = <2>; 798c2ecf20Sopenharmony_ci gpio-controller; 808c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 818c2ecf20Sopenharmony_ci interrupt-controller; 828c2ecf20Sopenharmony_ci 838c2ecf20Sopenharmony_ci touch_pins: touch_pins { 848c2ecf20Sopenharmony_ci pwr: pwr { 858c2ecf20Sopenharmony_ci pins = "gpio-0"; 868c2ecf20Sopenharmony_ci drive-strength = <16>; 878c2ecf20Sopenharmony_ci }; 888c2ecf20Sopenharmony_ci 898c2ecf20Sopenharmony_ci event: event { 908c2ecf20Sopenharmony_ci pins = "gpio-1"; 918c2ecf20Sopenharmony_ci bias-pull-up; 928c2ecf20Sopenharmony_ci }; 938c2ecf20Sopenharmony_ci }; 948c2ecf20Sopenharmony_ci }; 958c2ecf20Sopenharmony_ci 968c2ecf20Sopenharmony_ci gpio_asiu: gpio@180a5000 { 978c2ecf20Sopenharmony_ci compatible = "brcm,cygnus-asiu-gpio"; 988c2ecf20Sopenharmony_ci reg = <0x180a5000 0x668>; 998c2ecf20Sopenharmony_ci ngpios = <146>; 1008c2ecf20Sopenharmony_ci #gpio-cells = <2>; 1018c2ecf20Sopenharmony_ci gpio-controller; 1028c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1038c2ecf20Sopenharmony_ci interrupt-controller; 1048c2ecf20Sopenharmony_ci gpio-ranges = <&pinctrl 0 42 1>, 1058c2ecf20Sopenharmony_ci <&pinctrl 1 44 3>; 1068c2ecf20Sopenharmony_ci }; 1078c2ecf20Sopenharmony_ci 1088c2ecf20Sopenharmony_ci /* 1098c2ecf20Sopenharmony_ci * Touchscreen that uses the CCM GPIO 0 and 1 1108c2ecf20Sopenharmony_ci */ 1118c2ecf20Sopenharmony_ci tsc { 1128c2ecf20Sopenharmony_ci ... 1138c2ecf20Sopenharmony_ci ... 1148c2ecf20Sopenharmony_ci gpio-pwr = <&gpio_ccm 0 0>; 1158c2ecf20Sopenharmony_ci gpio-event = <&gpio_ccm 1 0>; 1168c2ecf20Sopenharmony_ci }; 1178c2ecf20Sopenharmony_ci 1188c2ecf20Sopenharmony_ci /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */ 1198c2ecf20Sopenharmony_ci bluetooth { 1208c2ecf20Sopenharmony_ci ... 1218c2ecf20Sopenharmony_ci ... 1228c2ecf20Sopenharmony_ci bcm,rfkill-bank-sel = <&gpio_asiu 5 1> 1238c2ecf20Sopenharmony_ci } 124