18c2ecf20Sopenharmony_ciRockchip PCIE PHY
28c2ecf20Sopenharmony_ci-----------------------
38c2ecf20Sopenharmony_ci
48c2ecf20Sopenharmony_ciRequired properties:
58c2ecf20Sopenharmony_ci - compatible: rockchip,rk3399-pcie-phy
68c2ecf20Sopenharmony_ci - clocks: Must contain an entry in clock-names.
78c2ecf20Sopenharmony_ci	See ../clocks/clock-bindings.txt for details.
88c2ecf20Sopenharmony_ci - clock-names: Must be "refclk"
98c2ecf20Sopenharmony_ci - resets: Must contain an entry in reset-names.
108c2ecf20Sopenharmony_ci	See ../reset/reset.txt for details.
118c2ecf20Sopenharmony_ci - reset-names: Must be "phy"
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ciRequired properties for legacy PHY mode (deprecated):
148c2ecf20Sopenharmony_ci - #phy-cells: must be 0
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ciRequired properties for per-lane PHY mode (preferred):
178c2ecf20Sopenharmony_ci - #phy-cells: must be 1
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ciExample:
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_cigrf: syscon@ff770000 {
228c2ecf20Sopenharmony_ci	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
238c2ecf20Sopenharmony_ci	#address-cells = <1>;
248c2ecf20Sopenharmony_ci	#size-cells = <1>;
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ci	...
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ci	pcie_phy: pcie-phy {
298c2ecf20Sopenharmony_ci		compatible = "rockchip,rk3399-pcie-phy";
308c2ecf20Sopenharmony_ci		#phy-cells = <0>;
318c2ecf20Sopenharmony_ci		clocks = <&cru SCLK_PCIEPHY_REF>;
328c2ecf20Sopenharmony_ci		clock-names = "refclk";
338c2ecf20Sopenharmony_ci		resets = <&cru SRST_PCIEPHY>;
348c2ecf20Sopenharmony_ci		reset-names = "phy";
358c2ecf20Sopenharmony_ci	};
368c2ecf20Sopenharmony_ci};
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