18c2ecf20Sopenharmony_ciRockchip EMMC PHY
28c2ecf20Sopenharmony_ci-----------------------
38c2ecf20Sopenharmony_ci
48c2ecf20Sopenharmony_ciRequired properties:
58c2ecf20Sopenharmony_ci - compatible: rockchip,rk3399-emmc-phy
68c2ecf20Sopenharmony_ci - #phy-cells: must be 0
78c2ecf20Sopenharmony_ci - reg: PHY register address offset and length in "general
88c2ecf20Sopenharmony_ci   register files"
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ciOptional properties:
118c2ecf20Sopenharmony_ci - clock-names: Should contain "emmcclk".  Although this is listed as optional
128c2ecf20Sopenharmony_ci		(because most boards can get basic functionality without having
138c2ecf20Sopenharmony_ci		access to it), it is strongly suggested.
148c2ecf20Sopenharmony_ci		See ../clock/clock-bindings.txt for details.
158c2ecf20Sopenharmony_ci - clocks: Should have a phandle to the card clock exported by the SDHCI driver.
168c2ecf20Sopenharmony_ci - drive-impedance-ohm: Specifies the drive impedance in Ohm.
178c2ecf20Sopenharmony_ci                        Possible values are 33, 40, 50, 66 and 100.
188c2ecf20Sopenharmony_ci                        If not set, the default value of 50 will be applied.
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ciExample:
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_cigrf: syscon@ff770000 {
248c2ecf20Sopenharmony_ci	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
258c2ecf20Sopenharmony_ci	#address-cells = <1>;
268c2ecf20Sopenharmony_ci	#size-cells = <1>;
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ci...
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci	emmcphy: phy@f780 {
318c2ecf20Sopenharmony_ci		compatible = "rockchip,rk3399-emmc-phy";
328c2ecf20Sopenharmony_ci		reg = <0xf780 0x20>;
338c2ecf20Sopenharmony_ci		clocks = <&sdhci>;
348c2ecf20Sopenharmony_ci		clock-names = "emmcclk";
358c2ecf20Sopenharmony_ci		drive-impedance-ohm = <50>;
368c2ecf20Sopenharmony_ci		#phy-cells = <0>;
378c2ecf20Sopenharmony_ci	};
388c2ecf20Sopenharmony_ci};
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