18c2ecf20Sopenharmony_ciRockchip specific extensions to the Analogix Display Port PHY 28c2ecf20Sopenharmony_ci------------------------------------ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciRequired properties: 58c2ecf20Sopenharmony_ci- compatible : should be one of the following supported values: 68c2ecf20Sopenharmony_ci - "rockchip.rk3288-dp-phy" 78c2ecf20Sopenharmony_ci- clocks: from common clock binding: handle to dp clock. 88c2ecf20Sopenharmony_ci of memory mapped region. 98c2ecf20Sopenharmony_ci- clock-names: from common clock binding: 108c2ecf20Sopenharmony_ci Required elements: "24m" 118c2ecf20Sopenharmony_ci- #phy-cells : from the generic PHY bindings, must be 0; 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ciExample: 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_cigrf: syscon@ff770000 { 168c2ecf20Sopenharmony_ci compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci... 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci edp_phy: edp-phy { 218c2ecf20Sopenharmony_ci compatible = "rockchip,rk3288-dp-phy"; 228c2ecf20Sopenharmony_ci clocks = <&cru SCLK_EDP_24M>; 238c2ecf20Sopenharmony_ci clock-names = "24m"; 248c2ecf20Sopenharmony_ci #phy-cells = <0>; 258c2ecf20Sopenharmony_ci }; 268c2ecf20Sopenharmony_ci}; 27