18c2ecf20Sopenharmony_ciQualcomm PCIe2 PHY controller
28c2ecf20Sopenharmony_ci=============================
38c2ecf20Sopenharmony_ci
48c2ecf20Sopenharmony_ciThe Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
58c2ecf20Sopenharmony_ciplatforms.
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciRequired properties:
88c2ecf20Sopenharmony_ci - compatible: compatible list, should be:
98c2ecf20Sopenharmony_ci	       "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ci - reg: offset and length of the PHY register set.
128c2ecf20Sopenharmony_ci - #phy-cells: must be 0.
138c2ecf20Sopenharmony_ci
148c2ecf20Sopenharmony_ci - clocks: a clock-specifier pair for the "pipe" clock
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ci - vdda-vp-supply: phandle to low voltage regulator
178c2ecf20Sopenharmony_ci - vdda-vph-supply: phandle to high voltage regulator
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci - resets: reset-specifier pairs for the "phy" and "pipe" resets
208c2ecf20Sopenharmony_ci - reset-names: list of resets, should contain:
218c2ecf20Sopenharmony_ci		"phy" and "pipe"
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci - clock-output-names: name of the outgoing clock signal from the PHY PLL
248c2ecf20Sopenharmony_ci - #clock-cells: must be 0
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ciExample:
278c2ecf20Sopenharmony_ci phy@7786000 {
288c2ecf20Sopenharmony_ci	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
298c2ecf20Sopenharmony_ci	reg = <0x07786000 0xb8>;
308c2ecf20Sopenharmony_ci
318c2ecf20Sopenharmony_ci	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
328c2ecf20Sopenharmony_ci	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
338c2ecf20Sopenharmony_ci	         <&gcc GCC_PCIE_0_PIPE_ARES>;
348c2ecf20Sopenharmony_ci	reset-names = "phy", "pipe";
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_ci	vdda-vp-supply = <&vreg_l3_1p05>;
378c2ecf20Sopenharmony_ci	vdda-vph-supply = <&vreg_l5_1p8>;
388c2ecf20Sopenharmony_ci
398c2ecf20Sopenharmony_ci	clock-output-names = "pcie_0_pipe_clk";
408c2ecf20Sopenharmony_ci	#clock-cells = <0>;
418c2ecf20Sopenharmony_ci	#phy-cells = <0>;
428c2ecf20Sopenharmony_ci };
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