18c2ecf20Sopenharmony_ciQualcomm APQ8064 SATA PHY Controller
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38c2ecf20Sopenharmony_ci
48c2ecf20Sopenharmony_ciSATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
58c2ecf20Sopenharmony_ciEach SATA PHY controller should have its own node.
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78c2ecf20Sopenharmony_ciRequired properties:
88c2ecf20Sopenharmony_ci- compatible: compatible list, contains "qcom,apq8064-sata-phy".
98c2ecf20Sopenharmony_ci- reg: offset and length of the SATA PHY register set;
108c2ecf20Sopenharmony_ci- #phy-cells: must be zero
118c2ecf20Sopenharmony_ci- clocks: a list of phandles and clock-specifier pairs, one for each entry in
128c2ecf20Sopenharmony_ci  clock-names.
138c2ecf20Sopenharmony_ci- clock-names: must be "cfg" for phy config clock.
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158c2ecf20Sopenharmony_ciExample:
168c2ecf20Sopenharmony_ci	sata_phy: sata-phy@1b400000 {
178c2ecf20Sopenharmony_ci		compatible = "qcom,apq8064-sata-phy";
188c2ecf20Sopenharmony_ci		reg = <0x1b400000 0x200>;
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ci		clocks = <&gcc SATA_PHY_CFG_CLK>;
218c2ecf20Sopenharmony_ci		clock-names = "cfg";
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci		#phy-cells = <0>;
248c2ecf20Sopenharmony_ci	};
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