18c2ecf20Sopenharmony_ciSTMicroelectronics STM32 USB HS PHY controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThe STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
48c2ecf20Sopenharmony_ciswitch. It controls PHY configuration and status, and the UTMI+ switch that
58c2ecf20Sopenharmony_ciselects either OTG or HOST controller for the second PHY port. It also sets
68c2ecf20Sopenharmony_ciPLL configuration.
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ciUSBPHYC
98c2ecf20Sopenharmony_ci      |_ PLL
108c2ecf20Sopenharmony_ci      |
118c2ecf20Sopenharmony_ci      |_ PHY port#1 _________________ HOST controller
128c2ecf20Sopenharmony_ci      |                    _                 |
138c2ecf20Sopenharmony_ci      |                  / 1|________________|
148c2ecf20Sopenharmony_ci      |_ PHY port#2 ----|   |________________
158c2ecf20Sopenharmony_ci      |                  \_0|                |
168c2ecf20Sopenharmony_ci      |_ UTMI switch_______|          OTG controller
178c2ecf20Sopenharmony_ci
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ciPhy provider node
208c2ecf20Sopenharmony_ci=================
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ciRequired properties:
238c2ecf20Sopenharmony_ci- compatible: must be "st,stm32mp1-usbphyc"
248c2ecf20Sopenharmony_ci- reg: address and length of the usb phy control register set
258c2ecf20Sopenharmony_ci- clocks: phandle + clock specifier for the PLL phy clock
268c2ecf20Sopenharmony_ci- #address-cells: number of address cells for phys sub-nodes, must be <1>
278c2ecf20Sopenharmony_ci- #size-cells: number of size cells for phys sub-nodes, must be <0>
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ciOptional properties:
308c2ecf20Sopenharmony_ci- assigned-clocks: phandle + clock specifier for the PLL phy clock
318c2ecf20Sopenharmony_ci- assigned-clock-parents: the PLL phy clock parent
328c2ecf20Sopenharmony_ci- resets: phandle + reset specifier
338c2ecf20Sopenharmony_ci
348c2ecf20Sopenharmony_ciRequired nodes: one sub-node per port the controller provides.
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_ciPhy sub-nodes
378c2ecf20Sopenharmony_ci==============
388c2ecf20Sopenharmony_ci
398c2ecf20Sopenharmony_ciRequired properties:
408c2ecf20Sopenharmony_ci- reg: phy port index
418c2ecf20Sopenharmony_ci- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
428c2ecf20Sopenharmony_ci	      see phy-bindings.txt in the same directory.
438c2ecf20Sopenharmony_ci- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
448c2ecf20Sopenharmony_ci- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
458c2ecf20Sopenharmony_ci- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
468c2ecf20Sopenharmony_ci  port#1 and must be <1> for PHY port#2, to select USB controller
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_ciExample:
508c2ecf20Sopenharmony_ci		usbphyc: usb-phy@5a006000 {
518c2ecf20Sopenharmony_ci			compatible = "st,stm32mp1-usbphyc";
528c2ecf20Sopenharmony_ci			reg = <0x5a006000 0x1000>;
538c2ecf20Sopenharmony_ci			clocks = <&rcc_clk USBPHY_K>;
548c2ecf20Sopenharmony_ci			resets = <&rcc_rst USBPHY_R>;
558c2ecf20Sopenharmony_ci			#address-cells = <1>;
568c2ecf20Sopenharmony_ci			#size-cells = <0>;
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ci			usbphyc_port0: usb-phy@0 {
598c2ecf20Sopenharmony_ci				reg = <0>;
608c2ecf20Sopenharmony_ci				phy-supply = <&vdd_usb>;
618c2ecf20Sopenharmony_ci				vdda1v1-supply = <&reg11>;
628c2ecf20Sopenharmony_ci				vdda1v8-supply = <&reg18>
638c2ecf20Sopenharmony_ci				#phy-cells = <0>;
648c2ecf20Sopenharmony_ci			};
658c2ecf20Sopenharmony_ci
668c2ecf20Sopenharmony_ci			usbphyc_port1: usb-phy@1 {
678c2ecf20Sopenharmony_ci				reg = <1>;
688c2ecf20Sopenharmony_ci				phy-supply = <&vdd_usb>;
698c2ecf20Sopenharmony_ci				vdda1v1-supply = <&reg11>;
708c2ecf20Sopenharmony_ci				vdda1v8-supply = <&reg18>
718c2ecf20Sopenharmony_ci				#phy-cells = <1>;
728c2ecf20Sopenharmony_ci			};
738c2ecf20Sopenharmony_ci		};
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