18c2ecf20Sopenharmony_ciLantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
28c2ecf20Sopenharmony_ci===========================================
38c2ecf20Sopenharmony_ci
48c2ecf20Sopenharmony_ciThis binding describes the USB PHY hardware provided by the RCU module on the
58c2ecf20Sopenharmony_ciLantiq XWAY SoCs.
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciThis node has to be a sub node of the Lantiq RCU block.
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ci-------------------------------------------------------------------------------
108c2ecf20Sopenharmony_ciRequired properties (controller (parent) node):
118c2ecf20Sopenharmony_ci- compatible	: Should be one of
128c2ecf20Sopenharmony_ci			"lantiq,ase-usb2-phy"
138c2ecf20Sopenharmony_ci			"lantiq,danube-usb2-phy"
148c2ecf20Sopenharmony_ci			"lantiq,xrx100-usb2-phy"
158c2ecf20Sopenharmony_ci			"lantiq,xrx200-usb2-phy"
168c2ecf20Sopenharmony_ci			"lantiq,xrx300-usb2-phy"
178c2ecf20Sopenharmony_ci- reg		: Defines the following sets of registers in the parent
188c2ecf20Sopenharmony_ci		  syscon device
198c2ecf20Sopenharmony_ci			- Offset of the USB PHY configuration register
208c2ecf20Sopenharmony_ci			- Offset of the USB Analog configuration
218c2ecf20Sopenharmony_ci			  register (only for xrx200 and xrx200)
228c2ecf20Sopenharmony_ci- clocks	: References to the (PMU) "phy" clk gate.
238c2ecf20Sopenharmony_ci- clock-names	: Must be "phy"
248c2ecf20Sopenharmony_ci- resets	: References to the RCU USB configuration reset bits.
258c2ecf20Sopenharmony_ci- reset-names	: Must be one of the following:
268c2ecf20Sopenharmony_ci			"phy" (optional)
278c2ecf20Sopenharmony_ci			"ctrl" (shared)
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci-------------------------------------------------------------------------------
308c2ecf20Sopenharmony_ciExample for the USB PHYs on an xRX200 SoC:
318c2ecf20Sopenharmony_ci	usb_phy0: usb2-phy@18 {
328c2ecf20Sopenharmony_ci		compatible = "lantiq,xrx200-usb2-phy";
338c2ecf20Sopenharmony_ci		reg = <0x18 4>, <0x38 4>;
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ci		clocks = <&pmu PMU_GATE_USB0_PHY>;
368c2ecf20Sopenharmony_ci		clock-names = "phy";
378c2ecf20Sopenharmony_ci		resets = <&reset1 4 4>, <&reset0 4 4>;
388c2ecf20Sopenharmony_ci		reset-names = "phy", "ctrl";
398c2ecf20Sopenharmony_ci		#phy-cells = <0>;
408c2ecf20Sopenharmony_ci	};
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