18c2ecf20Sopenharmony_ciDevice tree bindings for HiSilicon INNO USB2 PHY
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible: Should be one of the following strings:
58c2ecf20Sopenharmony_ci	"hisilicon,inno-usb2-phy",
68c2ecf20Sopenharmony_ci	"hisilicon,hi3798cv200-usb2-phy".
78c2ecf20Sopenharmony_ci- reg: Should be the address space for PHY configuration register in peripheral
88c2ecf20Sopenharmony_ci  controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
98c2ecf20Sopenharmony_ci- clocks: The phandle and clock specifier pair for INNO USB2 PHY device
108c2ecf20Sopenharmony_ci  reference clock.
118c2ecf20Sopenharmony_ci- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
128c2ecf20Sopenharmony_ci  signal.
138c2ecf20Sopenharmony_ci- #address-cells: Must be 1.
148c2ecf20Sopenharmony_ci- #size-cells: Must be 0.
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ciThe INNO USB2 PHY device should be a child node of peripheral controller that
178c2ecf20Sopenharmony_cicontains the PHY configuration register, and each device suppports up to 2 PHY
188c2ecf20Sopenharmony_ciports which are represented as child nodes of INNO USB2 PHY device.
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ciRequired properties for PHY port node:
218c2ecf20Sopenharmony_ci- reg: The PHY port instance number.
228c2ecf20Sopenharmony_ci- #phy-cells: Defined by generic PHY bindings.  Must be 0.
238c2ecf20Sopenharmony_ci- resets: The phandle and reset specifier pair for PHY port reset signal.
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_ciRefer to phy/phy-bindings.txt for the generic PHY binding properties
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ciExample:
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ciperictrl: peripheral-controller@8a20000 {
308c2ecf20Sopenharmony_ci	compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
318c2ecf20Sopenharmony_ci	reg = <0x8a20000 0x1000>;
328c2ecf20Sopenharmony_ci	#address-cells = <1>;
338c2ecf20Sopenharmony_ci	#size-cells = <1>;
348c2ecf20Sopenharmony_ci	ranges = <0x0 0x8a20000 0x1000>;
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_ci	usb2_phy1: usb2-phy@120 {
378c2ecf20Sopenharmony_ci		compatible = "hisilicon,hi3798cv200-usb2-phy";
388c2ecf20Sopenharmony_ci		reg = <0x120 0x4>;
398c2ecf20Sopenharmony_ci		clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
408c2ecf20Sopenharmony_ci		resets = <&crg 0xbc 4>;
418c2ecf20Sopenharmony_ci		#address-cells = <1>;
428c2ecf20Sopenharmony_ci		#size-cells = <0>;
438c2ecf20Sopenharmony_ci
448c2ecf20Sopenharmony_ci		usb2_phy1_port0: phy@0 {
458c2ecf20Sopenharmony_ci			reg = <0>;
468c2ecf20Sopenharmony_ci			#phy-cells = <0>;
478c2ecf20Sopenharmony_ci			resets = <&crg 0xbc 8>;
488c2ecf20Sopenharmony_ci		};
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_ci		usb2_phy1_port1: phy@1 {
518c2ecf20Sopenharmony_ci			reg = <1>;
528c2ecf20Sopenharmony_ci			#phy-cells = <0>;
538c2ecf20Sopenharmony_ci			resets = <&crg 0xbc 9>;
548c2ecf20Sopenharmony_ci		};
558c2ecf20Sopenharmony_ci	};
568c2ecf20Sopenharmony_ci
578c2ecf20Sopenharmony_ci	usb2_phy2: usb2-phy@124 {
588c2ecf20Sopenharmony_ci		compatible = "hisilicon,hi3798cv200-usb2-phy";
598c2ecf20Sopenharmony_ci		reg = <0x124 0x4>;
608c2ecf20Sopenharmony_ci		clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
618c2ecf20Sopenharmony_ci		resets = <&crg 0xbc 6>;
628c2ecf20Sopenharmony_ci		#address-cells = <1>;
638c2ecf20Sopenharmony_ci		#size-cells = <0>;
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_ci		usb2_phy2_port0: phy@0 {
668c2ecf20Sopenharmony_ci			reg = <0>;
678c2ecf20Sopenharmony_ci			#phy-cells = <0>;
688c2ecf20Sopenharmony_ci			resets = <&crg 0xbc 10>;
698c2ecf20Sopenharmony_ci		};
708c2ecf20Sopenharmony_ci	};
718c2ecf20Sopenharmony_ci};
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