18c2ecf20Sopenharmony_ci* Axis ARTPEC-6 PCIe interface 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis PCIe host controller is based on the Synopsys DesignWare PCIe IP 48c2ecf20Sopenharmony_ciand thus inherits all the common properties defined in designware-pcie.txt. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired properties: 78c2ecf20Sopenharmony_ci- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; 88c2ecf20Sopenharmony_ci "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; 98c2ecf20Sopenharmony_ci "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode; 108c2ecf20Sopenharmony_ci "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode; 118c2ecf20Sopenharmony_ci- reg: base addresses and lengths of the PCIe controller (DBI), 128c2ecf20Sopenharmony_ci the PHY controller, and configuration address space. 138c2ecf20Sopenharmony_ci- reg-names: Must include the following entries: 148c2ecf20Sopenharmony_ci - "dbi" 158c2ecf20Sopenharmony_ci - "phy" 168c2ecf20Sopenharmony_ci - "config" 178c2ecf20Sopenharmony_ci- interrupts: A list of interrupt outputs of the controller. Must contain an 188c2ecf20Sopenharmony_ci entry for each entry in the interrupt-names property. 198c2ecf20Sopenharmony_ci- interrupt-names: Must include the following entries: 208c2ecf20Sopenharmony_ci - "msi": The interrupt that is asserted when an MSI is received 218c2ecf20Sopenharmony_ci- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller, 228c2ecf20Sopenharmony_ci used to enable and control the Synopsys IP. 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ciExample: 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci pcie@f8050000 { 278c2ecf20Sopenharmony_ci compatible = "axis,artpec6-pcie", "snps,dw-pcie"; 288c2ecf20Sopenharmony_ci reg = <0xf8050000 0x2000 298c2ecf20Sopenharmony_ci 0xf8040000 0x1000 308c2ecf20Sopenharmony_ci 0xc0000000 0x2000>; 318c2ecf20Sopenharmony_ci reg-names = "dbi", "phy", "config"; 328c2ecf20Sopenharmony_ci #address-cells = <3>; 338c2ecf20Sopenharmony_ci #size-cells = <2>; 348c2ecf20Sopenharmony_ci device_type = "pci"; 358c2ecf20Sopenharmony_ci /* downstream I/O */ 368c2ecf20Sopenharmony_ci ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 378c2ecf20Sopenharmony_ci /* non-prefetchable memory */ 388c2ecf20Sopenharmony_ci 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; 398c2ecf20Sopenharmony_ci num-lanes = <2>; 408c2ecf20Sopenharmony_ci bus-range = <0x00 0xff>; 418c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 428c2ecf20Sopenharmony_ci interrupt-names = "msi"; 438c2ecf20Sopenharmony_ci #interrupt-cells = <1>; 448c2ecf20Sopenharmony_ci interrupt-map-mask = <0 0 0 0x7>; 458c2ecf20Sopenharmony_ci interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 468c2ecf20Sopenharmony_ci <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 478c2ecf20Sopenharmony_ci <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 488c2ecf20Sopenharmony_ci <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 498c2ecf20Sopenharmony_ci axis,syscon-pcie = <&syscon>; 508c2ecf20Sopenharmony_ci }; 51