18c2ecf20Sopenharmony_ciGeneric OPP (Operating Performance Points) Bindings 28c2ecf20Sopenharmony_ci---------------------------------------------------- 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciDevices work at voltage-current-frequency combinations and some implementations 58c2ecf20Sopenharmony_cihave the liberty of choosing these. These combinations are called Operating 68c2ecf20Sopenharmony_ciPerformance Points aka OPPs. This document defines bindings for these OPPs 78c2ecf20Sopenharmony_ciapplicable across wide range of devices. For illustration purpose, this document 88c2ecf20Sopenharmony_ciuses CPU as a device. 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ciThis document contain multiple versions of OPP binding and only one of them 118c2ecf20Sopenharmony_cishould be used per device. 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ciBinding 1: operating-points 148c2ecf20Sopenharmony_ci============================ 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciThis binding only supports voltage-frequency pairs. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciProperties: 198c2ecf20Sopenharmony_ci- operating-points: An array of 2-tuples items, and each item consists 208c2ecf20Sopenharmony_ci of frequency and voltage like <freq-kHz vol-uV>. 218c2ecf20Sopenharmony_ci freq: clock frequency in kHz 228c2ecf20Sopenharmony_ci vol: voltage in microvolt 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ciExamples: 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_cicpu@0 { 278c2ecf20Sopenharmony_ci compatible = "arm,cortex-a9"; 288c2ecf20Sopenharmony_ci reg = <0>; 298c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 308c2ecf20Sopenharmony_ci operating-points = < 318c2ecf20Sopenharmony_ci /* kHz uV */ 328c2ecf20Sopenharmony_ci 792000 1100000 338c2ecf20Sopenharmony_ci 396000 950000 348c2ecf20Sopenharmony_ci 198000 850000 358c2ecf20Sopenharmony_ci >; 368c2ecf20Sopenharmony_ci}; 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ciBinding 2: operating-points-v2 408c2ecf20Sopenharmony_ci============================ 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci* Property: operating-points-v2 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ciDevices supporting OPPs must set their "operating-points-v2" property with 458c2ecf20Sopenharmony_ciphandle to a OPP table in their DT node. The OPP core will use this phandle to 468c2ecf20Sopenharmony_cifind the operating points for the device. 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ciThis can contain more than one phandle for power domain providers that provide 498c2ecf20Sopenharmony_cimultiple power domains. That is, one phandle for each power domain. If only one 508c2ecf20Sopenharmony_ciphandle is available, then the same OPP table will be used for all power domains 518c2ecf20Sopenharmony_ciprovided by the power domain provider. 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ciIf required, this can be extended for SoC vendor specific bindings. Such bindings 548c2ecf20Sopenharmony_cishould be documented as Documentation/devicetree/bindings/power/<vendor>-opp.txt 558c2ecf20Sopenharmony_ciand should have a compatible description like: "operating-points-v2-<vendor>". 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci* OPP Table Node 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ciThis describes the OPPs belonging to a device. This node can have following 608c2ecf20Sopenharmony_ciproperties: 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_ciRequired properties: 638c2ecf20Sopenharmony_ci- compatible: Allow OPPs to express their compatibility. It should be: 648c2ecf20Sopenharmony_ci "operating-points-v2". 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ci- OPP nodes: One or more OPP nodes describing voltage-current-frequency 678c2ecf20Sopenharmony_ci combinations. Their name isn't significant but their phandle can be used to 688c2ecf20Sopenharmony_ci reference an OPP. 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ciOptional properties: 718c2ecf20Sopenharmony_ci- opp-shared: Indicates that device nodes using this OPP Table Node's phandle 728c2ecf20Sopenharmony_ci switch their DVFS state together, i.e. they share clock/voltage/current lines. 738c2ecf20Sopenharmony_ci Missing property means devices have independent clock/voltage/current lines, 748c2ecf20Sopenharmony_ci but they share OPP tables. 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci- status: Marks the OPP table enabled/disabled. 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ci 798c2ecf20Sopenharmony_ci* OPP Node 808c2ecf20Sopenharmony_ci 818c2ecf20Sopenharmony_ciThis defines voltage-current-frequency combinations along with other related 828c2ecf20Sopenharmony_ciproperties. 838c2ecf20Sopenharmony_ci 848c2ecf20Sopenharmony_ciRequired properties: 858c2ecf20Sopenharmony_ci- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. This is a 868c2ecf20Sopenharmony_ci required property for all device nodes, unless another "required" property to 878c2ecf20Sopenharmony_ci uniquely identify the OPP nodes exists. Devices like power domains must have 888c2ecf20Sopenharmony_ci another (implementation dependent) property. 898c2ecf20Sopenharmony_ci 908c2ecf20Sopenharmony_ci- opp-peak-kBps: Peak bandwidth in kilobytes per second, expressed as an array 918c2ecf20Sopenharmony_ci of 32-bit big-endian integers. Each element of the array represents the 928c2ecf20Sopenharmony_ci peak bandwidth value of each interconnect path. The number of elements should 938c2ecf20Sopenharmony_ci match the number of interconnect paths. 948c2ecf20Sopenharmony_ci 958c2ecf20Sopenharmony_ciOptional properties: 968c2ecf20Sopenharmony_ci- opp-microvolt: voltage in micro Volts. 978c2ecf20Sopenharmony_ci 988c2ecf20Sopenharmony_ci A single regulator's voltage is specified with an array of size one or three. 998c2ecf20Sopenharmony_ci Single entry is for target voltage and three entries are for <target min max> 1008c2ecf20Sopenharmony_ci voltages. 1018c2ecf20Sopenharmony_ci 1028c2ecf20Sopenharmony_ci Entries for multiple regulators shall be provided in the same field separated 1038c2ecf20Sopenharmony_ci by angular brackets <>. The OPP binding doesn't provide any provisions to 1048c2ecf20Sopenharmony_ci relate the values to their power supplies or the order in which the supplies 1058c2ecf20Sopenharmony_ci need to be configured and that is left for the implementation specific 1068c2ecf20Sopenharmony_ci binding. 1078c2ecf20Sopenharmony_ci 1088c2ecf20Sopenharmony_ci Entries for all regulators shall be of the same size, i.e. either all use a 1098c2ecf20Sopenharmony_ci single value or triplets. 1108c2ecf20Sopenharmony_ci 1118c2ecf20Sopenharmony_ci- opp-microvolt-<name>: Named opp-microvolt property. This is exactly similar to 1128c2ecf20Sopenharmony_ci the above opp-microvolt property, but allows multiple voltage ranges to be 1138c2ecf20Sopenharmony_ci provided for the same OPP. At runtime, the platform can pick a <name> and 1148c2ecf20Sopenharmony_ci matching opp-microvolt-<name> property will be enabled for all OPPs. If the 1158c2ecf20Sopenharmony_ci platform doesn't pick a specific <name> or the <name> doesn't match with any 1168c2ecf20Sopenharmony_ci opp-microvolt-<name> properties, then opp-microvolt property shall be used, if 1178c2ecf20Sopenharmony_ci present. 1188c2ecf20Sopenharmony_ci 1198c2ecf20Sopenharmony_ci- opp-microamp: The maximum current drawn by the device in microamperes 1208c2ecf20Sopenharmony_ci considering system specific parameters (such as transients, process, aging, 1218c2ecf20Sopenharmony_ci maximum operating temperature range etc.) as necessary. This may be used to 1228c2ecf20Sopenharmony_ci set the most efficient regulator operating mode. 1238c2ecf20Sopenharmony_ci 1248c2ecf20Sopenharmony_ci Should only be set if opp-microvolt is set for the OPP. 1258c2ecf20Sopenharmony_ci 1268c2ecf20Sopenharmony_ci Entries for multiple regulators shall be provided in the same field separated 1278c2ecf20Sopenharmony_ci by angular brackets <>. If current values aren't required for a regulator, 1288c2ecf20Sopenharmony_ci then it shall be filled with 0. If current values aren't required for any of 1298c2ecf20Sopenharmony_ci the regulators, then this field is not required. The OPP binding doesn't 1308c2ecf20Sopenharmony_ci provide any provisions to relate the values to their power supplies or the 1318c2ecf20Sopenharmony_ci order in which the supplies need to be configured and that is left for the 1328c2ecf20Sopenharmony_ci implementation specific binding. 1338c2ecf20Sopenharmony_ci 1348c2ecf20Sopenharmony_ci- opp-microamp-<name>: Named opp-microamp property. Similar to 1358c2ecf20Sopenharmony_ci opp-microvolt-<name> property, but for microamp instead. 1368c2ecf20Sopenharmony_ci 1378c2ecf20Sopenharmony_ci- opp-level: A value representing the performance level of the device, 1388c2ecf20Sopenharmony_ci expressed as a 32-bit integer. 1398c2ecf20Sopenharmony_ci 1408c2ecf20Sopenharmony_ci- opp-avg-kBps: Average bandwidth in kilobytes per second, expressed as an array 1418c2ecf20Sopenharmony_ci of 32-bit big-endian integers. Each element of the array represents the 1428c2ecf20Sopenharmony_ci average bandwidth value of each interconnect path. The number of elements 1438c2ecf20Sopenharmony_ci should match the number of interconnect paths. This property is only 1448c2ecf20Sopenharmony_ci meaningful in OPP tables where opp-peak-kBps is present. 1458c2ecf20Sopenharmony_ci 1468c2ecf20Sopenharmony_ci- clock-latency-ns: Specifies the maximum possible transition latency (in 1478c2ecf20Sopenharmony_ci nanoseconds) for switching to this OPP from any other OPP. 1488c2ecf20Sopenharmony_ci 1498c2ecf20Sopenharmony_ci- turbo-mode: Marks the OPP to be used only for turbo modes. Turbo mode is 1508c2ecf20Sopenharmony_ci available on some platforms, where the device can run over its operating 1518c2ecf20Sopenharmony_ci frequency for a short duration of time limited by the device's power, current 1528c2ecf20Sopenharmony_ci and thermal limits. 1538c2ecf20Sopenharmony_ci 1548c2ecf20Sopenharmony_ci- opp-suspend: Marks the OPP to be used during device suspend. If multiple OPPs 1558c2ecf20Sopenharmony_ci in the table have this, the OPP with highest opp-hz will be used. 1568c2ecf20Sopenharmony_ci 1578c2ecf20Sopenharmony_ci- opp-supported-hw: This property allows a platform to enable only a subset of 1588c2ecf20Sopenharmony_ci the OPPs from the larger set present in the OPP table, based on the current 1598c2ecf20Sopenharmony_ci version of the hardware (already known to the operating system). 1608c2ecf20Sopenharmony_ci 1618c2ecf20Sopenharmony_ci Each block present in the array of blocks in this property, represents a 1628c2ecf20Sopenharmony_ci sub-group of hardware versions supported by the OPP. i.e. <sub-group A>, 1638c2ecf20Sopenharmony_ci <sub-group B>, etc. The OPP will be enabled if _any_ of these sub-groups match 1648c2ecf20Sopenharmony_ci the hardware's version. 1658c2ecf20Sopenharmony_ci 1668c2ecf20Sopenharmony_ci Each sub-group is a platform defined array representing the hierarchy of 1678c2ecf20Sopenharmony_ci hardware versions supported by the platform. For a platform with three 1688c2ecf20Sopenharmony_ci hierarchical levels of version (X.Y.Z), this field shall look like 1698c2ecf20Sopenharmony_ci 1708c2ecf20Sopenharmony_ci opp-supported-hw = <X1 Y1 Z1>, <X2 Y2 Z2>, <X3 Y3 Z3>. 1718c2ecf20Sopenharmony_ci 1728c2ecf20Sopenharmony_ci Each level (eg. X1) in version hierarchy is represented by a 32 bit value, one 1738c2ecf20Sopenharmony_ci bit per version and so there can be maximum 32 versions per level. Logical AND 1748c2ecf20Sopenharmony_ci (&) operation is performed for each level with the hardware's level version 1758c2ecf20Sopenharmony_ci and a non-zero output for _all_ the levels in a sub-group means the OPP is 1768c2ecf20Sopenharmony_ci supported by hardware. A value of 0xFFFFFFFF for each level in the sub-group 1778c2ecf20Sopenharmony_ci will enable the OPP for all versions for the hardware. 1788c2ecf20Sopenharmony_ci 1798c2ecf20Sopenharmony_ci- status: Marks the node enabled/disabled. 1808c2ecf20Sopenharmony_ci 1818c2ecf20Sopenharmony_ci- required-opps: This contains phandle to an OPP node in another device's OPP 1828c2ecf20Sopenharmony_ci table. It may contain an array of phandles, where each phandle points to an 1838c2ecf20Sopenharmony_ci OPP of a different device. It should not contain multiple phandles to the OPP 1848c2ecf20Sopenharmony_ci nodes in the same OPP table. This specifies the minimum required OPP of the 1858c2ecf20Sopenharmony_ci device(s), whose OPP's phandle is present in this property, for the 1868c2ecf20Sopenharmony_ci functioning of the current device at the current OPP (where this property is 1878c2ecf20Sopenharmony_ci present). 1888c2ecf20Sopenharmony_ci 1898c2ecf20Sopenharmony_ciExample 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. 1908c2ecf20Sopenharmony_ci 1918c2ecf20Sopenharmony_ci/ { 1928c2ecf20Sopenharmony_ci cpus { 1938c2ecf20Sopenharmony_ci #address-cells = <1>; 1948c2ecf20Sopenharmony_ci #size-cells = <0>; 1958c2ecf20Sopenharmony_ci 1968c2ecf20Sopenharmony_ci cpu@0 { 1978c2ecf20Sopenharmony_ci compatible = "arm,cortex-a9"; 1988c2ecf20Sopenharmony_ci reg = <0>; 1998c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 2008c2ecf20Sopenharmony_ci clocks = <&clk_controller 0>; 2018c2ecf20Sopenharmony_ci clock-names = "cpu"; 2028c2ecf20Sopenharmony_ci cpu-supply = <&cpu_supply0>; 2038c2ecf20Sopenharmony_ci operating-points-v2 = <&cpu0_opp_table>; 2048c2ecf20Sopenharmony_ci }; 2058c2ecf20Sopenharmony_ci 2068c2ecf20Sopenharmony_ci cpu@1 { 2078c2ecf20Sopenharmony_ci compatible = "arm,cortex-a9"; 2088c2ecf20Sopenharmony_ci reg = <1>; 2098c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 2108c2ecf20Sopenharmony_ci clocks = <&clk_controller 0>; 2118c2ecf20Sopenharmony_ci clock-names = "cpu"; 2128c2ecf20Sopenharmony_ci cpu-supply = <&cpu_supply0>; 2138c2ecf20Sopenharmony_ci operating-points-v2 = <&cpu0_opp_table>; 2148c2ecf20Sopenharmony_ci }; 2158c2ecf20Sopenharmony_ci }; 2168c2ecf20Sopenharmony_ci 2178c2ecf20Sopenharmony_ci cpu0_opp_table: opp_table0 { 2188c2ecf20Sopenharmony_ci compatible = "operating-points-v2"; 2198c2ecf20Sopenharmony_ci opp-shared; 2208c2ecf20Sopenharmony_ci 2218c2ecf20Sopenharmony_ci opp-1000000000 { 2228c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1000000000>; 2238c2ecf20Sopenharmony_ci opp-microvolt = <975000 970000 985000>; 2248c2ecf20Sopenharmony_ci opp-microamp = <70000>; 2258c2ecf20Sopenharmony_ci clock-latency-ns = <300000>; 2268c2ecf20Sopenharmony_ci opp-suspend; 2278c2ecf20Sopenharmony_ci }; 2288c2ecf20Sopenharmony_ci opp-1100000000 { 2298c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1100000000>; 2308c2ecf20Sopenharmony_ci opp-microvolt = <1000000 980000 1010000>; 2318c2ecf20Sopenharmony_ci opp-microamp = <80000>; 2328c2ecf20Sopenharmony_ci clock-latency-ns = <310000>; 2338c2ecf20Sopenharmony_ci }; 2348c2ecf20Sopenharmony_ci opp-1200000000 { 2358c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1200000000>; 2368c2ecf20Sopenharmony_ci opp-microvolt = <1025000>; 2378c2ecf20Sopenharmony_ci clock-latency-ns = <290000>; 2388c2ecf20Sopenharmony_ci turbo-mode; 2398c2ecf20Sopenharmony_ci }; 2408c2ecf20Sopenharmony_ci }; 2418c2ecf20Sopenharmony_ci}; 2428c2ecf20Sopenharmony_ci 2438c2ecf20Sopenharmony_ciExample 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states 2448c2ecf20Sopenharmony_ciindependently. 2458c2ecf20Sopenharmony_ci 2468c2ecf20Sopenharmony_ci/ { 2478c2ecf20Sopenharmony_ci cpus { 2488c2ecf20Sopenharmony_ci #address-cells = <1>; 2498c2ecf20Sopenharmony_ci #size-cells = <0>; 2508c2ecf20Sopenharmony_ci 2518c2ecf20Sopenharmony_ci cpu@0 { 2528c2ecf20Sopenharmony_ci compatible = "qcom,krait"; 2538c2ecf20Sopenharmony_ci reg = <0>; 2548c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 2558c2ecf20Sopenharmony_ci clocks = <&clk_controller 0>; 2568c2ecf20Sopenharmony_ci clock-names = "cpu"; 2578c2ecf20Sopenharmony_ci cpu-supply = <&cpu_supply0>; 2588c2ecf20Sopenharmony_ci operating-points-v2 = <&cpu_opp_table>; 2598c2ecf20Sopenharmony_ci }; 2608c2ecf20Sopenharmony_ci 2618c2ecf20Sopenharmony_ci cpu@1 { 2628c2ecf20Sopenharmony_ci compatible = "qcom,krait"; 2638c2ecf20Sopenharmony_ci reg = <1>; 2648c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 2658c2ecf20Sopenharmony_ci clocks = <&clk_controller 1>; 2668c2ecf20Sopenharmony_ci clock-names = "cpu"; 2678c2ecf20Sopenharmony_ci cpu-supply = <&cpu_supply1>; 2688c2ecf20Sopenharmony_ci operating-points-v2 = <&cpu_opp_table>; 2698c2ecf20Sopenharmony_ci }; 2708c2ecf20Sopenharmony_ci 2718c2ecf20Sopenharmony_ci cpu@2 { 2728c2ecf20Sopenharmony_ci compatible = "qcom,krait"; 2738c2ecf20Sopenharmony_ci reg = <2>; 2748c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 2758c2ecf20Sopenharmony_ci clocks = <&clk_controller 2>; 2768c2ecf20Sopenharmony_ci clock-names = "cpu"; 2778c2ecf20Sopenharmony_ci cpu-supply = <&cpu_supply2>; 2788c2ecf20Sopenharmony_ci operating-points-v2 = <&cpu_opp_table>; 2798c2ecf20Sopenharmony_ci }; 2808c2ecf20Sopenharmony_ci 2818c2ecf20Sopenharmony_ci cpu@3 { 2828c2ecf20Sopenharmony_ci compatible = "qcom,krait"; 2838c2ecf20Sopenharmony_ci reg = <3>; 2848c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 2858c2ecf20Sopenharmony_ci clocks = <&clk_controller 3>; 2868c2ecf20Sopenharmony_ci clock-names = "cpu"; 2878c2ecf20Sopenharmony_ci cpu-supply = <&cpu_supply3>; 2888c2ecf20Sopenharmony_ci operating-points-v2 = <&cpu_opp_table>; 2898c2ecf20Sopenharmony_ci }; 2908c2ecf20Sopenharmony_ci }; 2918c2ecf20Sopenharmony_ci 2928c2ecf20Sopenharmony_ci cpu_opp_table: opp_table { 2938c2ecf20Sopenharmony_ci compatible = "operating-points-v2"; 2948c2ecf20Sopenharmony_ci 2958c2ecf20Sopenharmony_ci /* 2968c2ecf20Sopenharmony_ci * Missing opp-shared property means CPUs switch DVFS states 2978c2ecf20Sopenharmony_ci * independently. 2988c2ecf20Sopenharmony_ci */ 2998c2ecf20Sopenharmony_ci 3008c2ecf20Sopenharmony_ci opp-1000000000 { 3018c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1000000000>; 3028c2ecf20Sopenharmony_ci opp-microvolt = <975000 970000 985000>; 3038c2ecf20Sopenharmony_ci opp-microamp = <70000>; 3048c2ecf20Sopenharmony_ci clock-latency-ns = <300000>; 3058c2ecf20Sopenharmony_ci opp-suspend; 3068c2ecf20Sopenharmony_ci }; 3078c2ecf20Sopenharmony_ci opp-1100000000 { 3088c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1100000000>; 3098c2ecf20Sopenharmony_ci opp-microvolt = <1000000 980000 1010000>; 3108c2ecf20Sopenharmony_ci opp-microamp = <80000>; 3118c2ecf20Sopenharmony_ci clock-latency-ns = <310000>; 3128c2ecf20Sopenharmony_ci }; 3138c2ecf20Sopenharmony_ci opp-1200000000 { 3148c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1200000000>; 3158c2ecf20Sopenharmony_ci opp-microvolt = <1025000>; 3168c2ecf20Sopenharmony_ci opp-microamp = <90000; 3178c2ecf20Sopenharmony_ci lock-latency-ns = <290000>; 3188c2ecf20Sopenharmony_ci turbo-mode; 3198c2ecf20Sopenharmony_ci }; 3208c2ecf20Sopenharmony_ci }; 3218c2ecf20Sopenharmony_ci}; 3228c2ecf20Sopenharmony_ci 3238c2ecf20Sopenharmony_ciExample 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch 3248c2ecf20Sopenharmony_ciDVFS state together. 3258c2ecf20Sopenharmony_ci 3268c2ecf20Sopenharmony_ci/ { 3278c2ecf20Sopenharmony_ci cpus { 3288c2ecf20Sopenharmony_ci #address-cells = <1>; 3298c2ecf20Sopenharmony_ci #size-cells = <0>; 3308c2ecf20Sopenharmony_ci 3318c2ecf20Sopenharmony_ci cpu@0 { 3328c2ecf20Sopenharmony_ci compatible = "arm,cortex-a7"; 3338c2ecf20Sopenharmony_ci reg = <0>; 3348c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 3358c2ecf20Sopenharmony_ci clocks = <&clk_controller 0>; 3368c2ecf20Sopenharmony_ci clock-names = "cpu"; 3378c2ecf20Sopenharmony_ci cpu-supply = <&cpu_supply0>; 3388c2ecf20Sopenharmony_ci operating-points-v2 = <&cluster0_opp>; 3398c2ecf20Sopenharmony_ci }; 3408c2ecf20Sopenharmony_ci 3418c2ecf20Sopenharmony_ci cpu@1 { 3428c2ecf20Sopenharmony_ci compatible = "arm,cortex-a7"; 3438c2ecf20Sopenharmony_ci reg = <1>; 3448c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 3458c2ecf20Sopenharmony_ci clocks = <&clk_controller 0>; 3468c2ecf20Sopenharmony_ci clock-names = "cpu"; 3478c2ecf20Sopenharmony_ci cpu-supply = <&cpu_supply0>; 3488c2ecf20Sopenharmony_ci operating-points-v2 = <&cluster0_opp>; 3498c2ecf20Sopenharmony_ci }; 3508c2ecf20Sopenharmony_ci 3518c2ecf20Sopenharmony_ci cpu@100 { 3528c2ecf20Sopenharmony_ci compatible = "arm,cortex-a15"; 3538c2ecf20Sopenharmony_ci reg = <100>; 3548c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 3558c2ecf20Sopenharmony_ci clocks = <&clk_controller 1>; 3568c2ecf20Sopenharmony_ci clock-names = "cpu"; 3578c2ecf20Sopenharmony_ci cpu-supply = <&cpu_supply1>; 3588c2ecf20Sopenharmony_ci operating-points-v2 = <&cluster1_opp>; 3598c2ecf20Sopenharmony_ci }; 3608c2ecf20Sopenharmony_ci 3618c2ecf20Sopenharmony_ci cpu@101 { 3628c2ecf20Sopenharmony_ci compatible = "arm,cortex-a15"; 3638c2ecf20Sopenharmony_ci reg = <101>; 3648c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 3658c2ecf20Sopenharmony_ci clocks = <&clk_controller 1>; 3668c2ecf20Sopenharmony_ci clock-names = "cpu"; 3678c2ecf20Sopenharmony_ci cpu-supply = <&cpu_supply1>; 3688c2ecf20Sopenharmony_ci operating-points-v2 = <&cluster1_opp>; 3698c2ecf20Sopenharmony_ci }; 3708c2ecf20Sopenharmony_ci }; 3718c2ecf20Sopenharmony_ci 3728c2ecf20Sopenharmony_ci cluster0_opp: opp_table0 { 3738c2ecf20Sopenharmony_ci compatible = "operating-points-v2"; 3748c2ecf20Sopenharmony_ci opp-shared; 3758c2ecf20Sopenharmony_ci 3768c2ecf20Sopenharmony_ci opp-1000000000 { 3778c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1000000000>; 3788c2ecf20Sopenharmony_ci opp-microvolt = <975000 970000 985000>; 3798c2ecf20Sopenharmony_ci opp-microamp = <70000>; 3808c2ecf20Sopenharmony_ci clock-latency-ns = <300000>; 3818c2ecf20Sopenharmony_ci opp-suspend; 3828c2ecf20Sopenharmony_ci }; 3838c2ecf20Sopenharmony_ci opp-1100000000 { 3848c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1100000000>; 3858c2ecf20Sopenharmony_ci opp-microvolt = <1000000 980000 1010000>; 3868c2ecf20Sopenharmony_ci opp-microamp = <80000>; 3878c2ecf20Sopenharmony_ci clock-latency-ns = <310000>; 3888c2ecf20Sopenharmony_ci }; 3898c2ecf20Sopenharmony_ci opp-1200000000 { 3908c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1200000000>; 3918c2ecf20Sopenharmony_ci opp-microvolt = <1025000>; 3928c2ecf20Sopenharmony_ci opp-microamp = <90000>; 3938c2ecf20Sopenharmony_ci clock-latency-ns = <290000>; 3948c2ecf20Sopenharmony_ci turbo-mode; 3958c2ecf20Sopenharmony_ci }; 3968c2ecf20Sopenharmony_ci }; 3978c2ecf20Sopenharmony_ci 3988c2ecf20Sopenharmony_ci cluster1_opp: opp_table1 { 3998c2ecf20Sopenharmony_ci compatible = "operating-points-v2"; 4008c2ecf20Sopenharmony_ci opp-shared; 4018c2ecf20Sopenharmony_ci 4028c2ecf20Sopenharmony_ci opp-1300000000 { 4038c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1300000000>; 4048c2ecf20Sopenharmony_ci opp-microvolt = <1050000 1045000 1055000>; 4058c2ecf20Sopenharmony_ci opp-microamp = <95000>; 4068c2ecf20Sopenharmony_ci clock-latency-ns = <400000>; 4078c2ecf20Sopenharmony_ci opp-suspend; 4088c2ecf20Sopenharmony_ci }; 4098c2ecf20Sopenharmony_ci opp-1400000000 { 4108c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1400000000>; 4118c2ecf20Sopenharmony_ci opp-microvolt = <1075000>; 4128c2ecf20Sopenharmony_ci opp-microamp = <100000>; 4138c2ecf20Sopenharmony_ci clock-latency-ns = <400000>; 4148c2ecf20Sopenharmony_ci }; 4158c2ecf20Sopenharmony_ci opp-1500000000 { 4168c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1500000000>; 4178c2ecf20Sopenharmony_ci opp-microvolt = <1100000 1010000 1110000>; 4188c2ecf20Sopenharmony_ci opp-microamp = <95000>; 4198c2ecf20Sopenharmony_ci clock-latency-ns = <400000>; 4208c2ecf20Sopenharmony_ci turbo-mode; 4218c2ecf20Sopenharmony_ci }; 4228c2ecf20Sopenharmony_ci }; 4238c2ecf20Sopenharmony_ci}; 4248c2ecf20Sopenharmony_ci 4258c2ecf20Sopenharmony_ciExample 4: Handling multiple regulators 4268c2ecf20Sopenharmony_ci 4278c2ecf20Sopenharmony_ci/ { 4288c2ecf20Sopenharmony_ci cpus { 4298c2ecf20Sopenharmony_ci cpu@0 { 4308c2ecf20Sopenharmony_ci compatible = "vendor,cpu-type"; 4318c2ecf20Sopenharmony_ci ... 4328c2ecf20Sopenharmony_ci 4338c2ecf20Sopenharmony_ci vcc0-supply = <&cpu_supply0>; 4348c2ecf20Sopenharmony_ci vcc1-supply = <&cpu_supply1>; 4358c2ecf20Sopenharmony_ci vcc2-supply = <&cpu_supply2>; 4368c2ecf20Sopenharmony_ci operating-points-v2 = <&cpu0_opp_table>; 4378c2ecf20Sopenharmony_ci }; 4388c2ecf20Sopenharmony_ci }; 4398c2ecf20Sopenharmony_ci 4408c2ecf20Sopenharmony_ci cpu0_opp_table: opp_table0 { 4418c2ecf20Sopenharmony_ci compatible = "operating-points-v2"; 4428c2ecf20Sopenharmony_ci opp-shared; 4438c2ecf20Sopenharmony_ci 4448c2ecf20Sopenharmony_ci opp-1000000000 { 4458c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1000000000>; 4468c2ecf20Sopenharmony_ci opp-microvolt = <970000>, /* Supply 0 */ 4478c2ecf20Sopenharmony_ci <960000>, /* Supply 1 */ 4488c2ecf20Sopenharmony_ci <960000>; /* Supply 2 */ 4498c2ecf20Sopenharmony_ci opp-microamp = <70000>, /* Supply 0 */ 4508c2ecf20Sopenharmony_ci <70000>, /* Supply 1 */ 4518c2ecf20Sopenharmony_ci <70000>; /* Supply 2 */ 4528c2ecf20Sopenharmony_ci clock-latency-ns = <300000>; 4538c2ecf20Sopenharmony_ci }; 4548c2ecf20Sopenharmony_ci 4558c2ecf20Sopenharmony_ci /* OR */ 4568c2ecf20Sopenharmony_ci 4578c2ecf20Sopenharmony_ci opp-1000000000 { 4588c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1000000000>; 4598c2ecf20Sopenharmony_ci opp-microvolt = <975000 970000 985000>, /* Supply 0 */ 4608c2ecf20Sopenharmony_ci <965000 960000 975000>, /* Supply 1 */ 4618c2ecf20Sopenharmony_ci <965000 960000 975000>; /* Supply 2 */ 4628c2ecf20Sopenharmony_ci opp-microamp = <70000>, /* Supply 0 */ 4638c2ecf20Sopenharmony_ci <70000>, /* Supply 1 */ 4648c2ecf20Sopenharmony_ci <70000>; /* Supply 2 */ 4658c2ecf20Sopenharmony_ci clock-latency-ns = <300000>; 4668c2ecf20Sopenharmony_ci }; 4678c2ecf20Sopenharmony_ci 4688c2ecf20Sopenharmony_ci /* OR */ 4698c2ecf20Sopenharmony_ci 4708c2ecf20Sopenharmony_ci opp-1000000000 { 4718c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1000000000>; 4728c2ecf20Sopenharmony_ci opp-microvolt = <975000 970000 985000>, /* Supply 0 */ 4738c2ecf20Sopenharmony_ci <965000 960000 975000>, /* Supply 1 */ 4748c2ecf20Sopenharmony_ci <965000 960000 975000>; /* Supply 2 */ 4758c2ecf20Sopenharmony_ci opp-microamp = <70000>, /* Supply 0 */ 4768c2ecf20Sopenharmony_ci <0>, /* Supply 1 doesn't need this */ 4778c2ecf20Sopenharmony_ci <70000>; /* Supply 2 */ 4788c2ecf20Sopenharmony_ci clock-latency-ns = <300000>; 4798c2ecf20Sopenharmony_ci }; 4808c2ecf20Sopenharmony_ci }; 4818c2ecf20Sopenharmony_ci}; 4828c2ecf20Sopenharmony_ci 4838c2ecf20Sopenharmony_ciExample 5: opp-supported-hw 4848c2ecf20Sopenharmony_ci(example: three level hierarchy of versions: cuts, substrate and process) 4858c2ecf20Sopenharmony_ci 4868c2ecf20Sopenharmony_ci/ { 4878c2ecf20Sopenharmony_ci cpus { 4888c2ecf20Sopenharmony_ci cpu@0 { 4898c2ecf20Sopenharmony_ci compatible = "arm,cortex-a7"; 4908c2ecf20Sopenharmony_ci ... 4918c2ecf20Sopenharmony_ci 4928c2ecf20Sopenharmony_ci cpu-supply = <&cpu_supply> 4938c2ecf20Sopenharmony_ci operating-points-v2 = <&cpu0_opp_table_slow>; 4948c2ecf20Sopenharmony_ci }; 4958c2ecf20Sopenharmony_ci }; 4968c2ecf20Sopenharmony_ci 4978c2ecf20Sopenharmony_ci opp_table { 4988c2ecf20Sopenharmony_ci compatible = "operating-points-v2"; 4998c2ecf20Sopenharmony_ci opp-shared; 5008c2ecf20Sopenharmony_ci 5018c2ecf20Sopenharmony_ci opp-600000000 { 5028c2ecf20Sopenharmony_ci /* 5038c2ecf20Sopenharmony_ci * Supports all substrate and process versions for 0xF 5048c2ecf20Sopenharmony_ci * cuts, i.e. only first four cuts. 5058c2ecf20Sopenharmony_ci */ 5068c2ecf20Sopenharmony_ci opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF> 5078c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <600000000>; 5088c2ecf20Sopenharmony_ci ... 5098c2ecf20Sopenharmony_ci }; 5108c2ecf20Sopenharmony_ci 5118c2ecf20Sopenharmony_ci opp-800000000 { 5128c2ecf20Sopenharmony_ci /* 5138c2ecf20Sopenharmony_ci * Supports: 5148c2ecf20Sopenharmony_ci * - cuts: only one, 6th cut (represented by 6th bit). 5158c2ecf20Sopenharmony_ci * - substrate: supports 16 different substrate versions 5168c2ecf20Sopenharmony_ci * - process: supports 9 different process versions 5178c2ecf20Sopenharmony_ci */ 5188c2ecf20Sopenharmony_ci opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0> 5198c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <800000000>; 5208c2ecf20Sopenharmony_ci ... 5218c2ecf20Sopenharmony_ci }; 5228c2ecf20Sopenharmony_ci 5238c2ecf20Sopenharmony_ci opp-900000000 { 5248c2ecf20Sopenharmony_ci /* 5258c2ecf20Sopenharmony_ci * Supports: 5268c2ecf20Sopenharmony_ci * - All cuts and substrate where process version is 0x2. 5278c2ecf20Sopenharmony_ci * - All cuts and process where substrate version is 0x2. 5288c2ecf20Sopenharmony_ci */ 5298c2ecf20Sopenharmony_ci opp-supported-hw = <0xFFFFFFFF 0xFFFFFFFF 0x02>, <0xFFFFFFFF 0x01 0xFFFFFFFF> 5308c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <900000000>; 5318c2ecf20Sopenharmony_ci ... 5328c2ecf20Sopenharmony_ci }; 5338c2ecf20Sopenharmony_ci }; 5348c2ecf20Sopenharmony_ci}; 5358c2ecf20Sopenharmony_ci 5368c2ecf20Sopenharmony_ciExample 6: opp-microvolt-<name>, opp-microamp-<name>: 5378c2ecf20Sopenharmony_ci(example: device with two possible microvolt ranges: slow and fast) 5388c2ecf20Sopenharmony_ci 5398c2ecf20Sopenharmony_ci/ { 5408c2ecf20Sopenharmony_ci cpus { 5418c2ecf20Sopenharmony_ci cpu@0 { 5428c2ecf20Sopenharmony_ci compatible = "arm,cortex-a7"; 5438c2ecf20Sopenharmony_ci ... 5448c2ecf20Sopenharmony_ci 5458c2ecf20Sopenharmony_ci operating-points-v2 = <&cpu0_opp_table>; 5468c2ecf20Sopenharmony_ci }; 5478c2ecf20Sopenharmony_ci }; 5488c2ecf20Sopenharmony_ci 5498c2ecf20Sopenharmony_ci cpu0_opp_table: opp_table0 { 5508c2ecf20Sopenharmony_ci compatible = "operating-points-v2"; 5518c2ecf20Sopenharmony_ci opp-shared; 5528c2ecf20Sopenharmony_ci 5538c2ecf20Sopenharmony_ci opp-1000000000 { 5548c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1000000000>; 5558c2ecf20Sopenharmony_ci opp-microvolt-slow = <915000 900000 925000>; 5568c2ecf20Sopenharmony_ci opp-microvolt-fast = <975000 970000 985000>; 5578c2ecf20Sopenharmony_ci opp-microamp-slow = <70000>; 5588c2ecf20Sopenharmony_ci opp-microamp-fast = <71000>; 5598c2ecf20Sopenharmony_ci }; 5608c2ecf20Sopenharmony_ci 5618c2ecf20Sopenharmony_ci opp-1200000000 { 5628c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <1200000000>; 5638c2ecf20Sopenharmony_ci opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */ 5648c2ecf20Sopenharmony_ci <925000 910000 935000>; /* Supply vcc1 */ 5658c2ecf20Sopenharmony_ci opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */ 5668c2ecf20Sopenharmony_ci <965000 960000 975000>; /* Supply vcc1 */ 5678c2ecf20Sopenharmony_ci opp-microamp = <70000>; /* Will be used for both slow/fast */ 5688c2ecf20Sopenharmony_ci }; 5698c2ecf20Sopenharmony_ci }; 5708c2ecf20Sopenharmony_ci}; 571