18c2ecf20Sopenharmony_ciRockchip internal OTP (One Time Programmable) memory device tree bindings 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci- compatible: Should be one of the following. 58c2ecf20Sopenharmony_ci - "rockchip,px30-otp" - for PX30 SoCs. 68c2ecf20Sopenharmony_ci - "rockchip,rk3308-otp" - for RK3308 SoCs. 78c2ecf20Sopenharmony_ci- reg: Should contain the registers location and size 88c2ecf20Sopenharmony_ci- clocks: Must contain an entry for each entry in clock-names. 98c2ecf20Sopenharmony_ci- clock-names: Should be "otp", "apb_pclk" and "phy". 108c2ecf20Sopenharmony_ci- resets: Must contain an entry for each entry in reset-names. 118c2ecf20Sopenharmony_ci See ../../reset/reset.txt for details. 128c2ecf20Sopenharmony_ci- reset-names: Should be "phy". 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ciSee nvmem.txt for more information. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciExample: 178c2ecf20Sopenharmony_ci otp: otp@ff290000 { 188c2ecf20Sopenharmony_ci compatible = "rockchip,px30-otp"; 198c2ecf20Sopenharmony_ci reg = <0x0 0xff290000 0x0 0x4000>; 208c2ecf20Sopenharmony_ci #address-cells = <1>; 218c2ecf20Sopenharmony_ci #size-cells = <1>; 228c2ecf20Sopenharmony_ci clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 238c2ecf20Sopenharmony_ci <&cru PCLK_OTP_PHY>; 248c2ecf20Sopenharmony_ci clock-names = "otp", "apb_pclk", "phy"; 258c2ecf20Sopenharmony_ci }; 26