18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
28c2ecf20Sopenharmony_ci# Copyright (C) 2019 Texas Instruments Incorporated
38c2ecf20Sopenharmony_ci%YAML 1.2
48c2ecf20Sopenharmony_ci---
58c2ecf20Sopenharmony_ci$id: "http://devicetree.org/schemas/net/ti,dp83867.yaml#"
68c2ecf20Sopenharmony_ci$schema: "http://devicetree.org/meta-schemas/core.yaml#"
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_cititle: TI DP83867 ethernet PHY
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ciallOf:
118c2ecf20Sopenharmony_ci  - $ref: "ethernet-controller.yaml#"
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_cimaintainers:
148c2ecf20Sopenharmony_ci  - Dan Murphy <dmurphy@ti.com>
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_cidescription: |
178c2ecf20Sopenharmony_ci  The DP83867 device is a robust, low power, fully featured Physical Layer
188c2ecf20Sopenharmony_ci  transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
198c2ecf20Sopenharmony_ci  and 1000BASE-T Ethernet protocols.
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci  The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet
228c2ecf20Sopenharmony_ci  LANs. It interfaces directly to twisted pair media via an external
238c2ecf20Sopenharmony_ci  transformer. This device interfaces directly to the MAC layer through the
248c2ecf20Sopenharmony_ci  IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit
258c2ecf20Sopenharmony_ci  Media Independent Interface (GMII) or Reduced GMII (RGMII).
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ci  Specifications about the Ethernet PHY can be found at:
288c2ecf20Sopenharmony_ci    https://www.ti.com/lit/gpn/dp83867ir
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ciproperties:
318c2ecf20Sopenharmony_ci  reg:
328c2ecf20Sopenharmony_ci    maxItems: 1
338c2ecf20Sopenharmony_ci
348c2ecf20Sopenharmony_ci  ti,min-output-impedance:
358c2ecf20Sopenharmony_ci    type: boolean
368c2ecf20Sopenharmony_ci    description: |
378c2ecf20Sopenharmony_ci       MAC Interface Impedance control to set the programmable output impedance
388c2ecf20Sopenharmony_ci       to a minimum value (35 ohms).
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ci  ti,max-output-impedance:
418c2ecf20Sopenharmony_ci    type: boolean
428c2ecf20Sopenharmony_ci    description: |
438c2ecf20Sopenharmony_ci      MAC Interface Impedance control to set the programmable output impedance
448c2ecf20Sopenharmony_ci      to a maximum value (70 ohms).
458c2ecf20Sopenharmony_ci      Note: ti,min-output-impedance and ti,max-output-impedance are mutually
468c2ecf20Sopenharmony_ci        exclusive. When both properties are present ti,max-output-impedance
478c2ecf20Sopenharmony_ci        takes precedence.
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_ci  tx-fifo-depth:
508c2ecf20Sopenharmony_ci    $ref: /schemas/types.yaml#definitions/uint32
518c2ecf20Sopenharmony_ci    description: |
528c2ecf20Sopenharmony_ci       Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ci  rx-fifo-depth:
558c2ecf20Sopenharmony_ci    $ref: /schemas/types.yaml#definitions/uint32
568c2ecf20Sopenharmony_ci    description: |
578c2ecf20Sopenharmony_ci       Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values
588c2ecf20Sopenharmony_ci
598c2ecf20Sopenharmony_ci  ti,clk-output-sel:
608c2ecf20Sopenharmony_ci    $ref: /schemas/types.yaml#definitions/uint32
618c2ecf20Sopenharmony_ci    description: |
628c2ecf20Sopenharmony_ci      Muxing option for CLK_OUT pin.  See dt-bindings/net/ti-dp83867.h
638c2ecf20Sopenharmony_ci      for applicable values. The CLK_OUT pin can also be disabled by this
648c2ecf20Sopenharmony_ci      property.  When omitted, the PHY's default will be left as is.
658c2ecf20Sopenharmony_ci
668c2ecf20Sopenharmony_ci  ti,rx-internal-delay:
678c2ecf20Sopenharmony_ci    $ref: /schemas/types.yaml#definitions/uint32
688c2ecf20Sopenharmony_ci    description: |
698c2ecf20Sopenharmony_ci      RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
708c2ecf20Sopenharmony_ci      for applicable values. Required only if interface type is
718c2ecf20Sopenharmony_ci      PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID.
728c2ecf20Sopenharmony_ci
738c2ecf20Sopenharmony_ci  ti,tx-internal-delay:
748c2ecf20Sopenharmony_ci    $ref: /schemas/types.yaml#definitions/uint32
758c2ecf20Sopenharmony_ci    description: |
768c2ecf20Sopenharmony_ci      RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
778c2ecf20Sopenharmony_ci      for applicable values. Required only if interface type is
788c2ecf20Sopenharmony_ci      PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID.
798c2ecf20Sopenharmony_ci
808c2ecf20Sopenharmony_ci        Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock
818c2ecf20Sopenharmony_ci          delays will be left at their default values, as set by the PHY's pin
828c2ecf20Sopenharmony_ci          strapping. The default strapping will use a delay of 2.00 ns.  Thus
838c2ecf20Sopenharmony_ci          PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
848c2ecf20Sopenharmony_ci          internal delay, but as PHY_INTERFACE_MODE_RGMII_ID.  The device tree
858c2ecf20Sopenharmony_ci          should use "rgmii-id" if internal delays are desired as this may be
868c2ecf20Sopenharmony_ci          changed in future to cause "rgmii" mode to disable delays.
878c2ecf20Sopenharmony_ci
888c2ecf20Sopenharmony_ci  ti,dp83867-rxctrl-strap-quirk:
898c2ecf20Sopenharmony_ci    type: boolean
908c2ecf20Sopenharmony_ci    description: |
918c2ecf20Sopenharmony_ci      This denotes the fact that the board has RX_DV/RX_CTRL pin strapped in
928c2ecf20Sopenharmony_ci      mode 1 or 2. To ensure PHY operation, there are specific actions that
938c2ecf20Sopenharmony_ci      software needs to take when this pin is strapped in these modes.
948c2ecf20Sopenharmony_ci      See data manual for details.
958c2ecf20Sopenharmony_ci
968c2ecf20Sopenharmony_ci  ti,sgmii-ref-clock-output-enable:
978c2ecf20Sopenharmony_ci    type: boolean
988c2ecf20Sopenharmony_ci    description: |
998c2ecf20Sopenharmony_ci      This denotes which SGMII configuration is used (4 or 6-wire modes).
1008c2ecf20Sopenharmony_ci      Some MACs work with differential SGMII clock. See data manual for details.
1018c2ecf20Sopenharmony_ci
1028c2ecf20Sopenharmony_ci  ti,fifo-depth:
1038c2ecf20Sopenharmony_ci    deprecated: true
1048c2ecf20Sopenharmony_ci    $ref: /schemas/types.yaml#definitions/uint32
1058c2ecf20Sopenharmony_ci    description: |
1068c2ecf20Sopenharmony_ci      Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable
1078c2ecf20Sopenharmony_ci      values.
1088c2ecf20Sopenharmony_ci
1098c2ecf20Sopenharmony_cirequired:
1108c2ecf20Sopenharmony_ci  - reg
1118c2ecf20Sopenharmony_ci
1128c2ecf20Sopenharmony_ciunevaluatedProperties: false
1138c2ecf20Sopenharmony_ci
1148c2ecf20Sopenharmony_ciexamples:
1158c2ecf20Sopenharmony_ci  - |
1168c2ecf20Sopenharmony_ci    #include <dt-bindings/net/ti-dp83867.h>
1178c2ecf20Sopenharmony_ci    mdio0 {
1188c2ecf20Sopenharmony_ci      #address-cells = <1>;
1198c2ecf20Sopenharmony_ci      #size-cells = <0>;
1208c2ecf20Sopenharmony_ci      ethphy0: ethernet-phy@0 {
1218c2ecf20Sopenharmony_ci        reg = <0>;
1228c2ecf20Sopenharmony_ci        tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
1238c2ecf20Sopenharmony_ci        rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
1248c2ecf20Sopenharmony_ci        ti,max-output-impedance;
1258c2ecf20Sopenharmony_ci        ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
1268c2ecf20Sopenharmony_ci        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
1278c2ecf20Sopenharmony_ci        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
1288c2ecf20Sopenharmony_ci      };
1298c2ecf20Sopenharmony_ci    };
130