18c2ecf20Sopenharmony_ci* Microchip ENC28J60 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis is a standalone 10 MBit ethernet controller with SPI interface. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciFor each device connected to a SPI bus, define a child node within 68c2ecf20Sopenharmony_cithe SPI master node. 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciRequired properties: 98c2ecf20Sopenharmony_ci- compatible: Should be "microchip,enc28j60" 108c2ecf20Sopenharmony_ci- reg: Specify the SPI chip select the ENC28J60 is wired to 118c2ecf20Sopenharmony_ci- interrupts: Specify the interrupt index within the interrupt controller (referred 128c2ecf20Sopenharmony_ci to above in interrupt-parent) and interrupt type. The ENC28J60 natively 138c2ecf20Sopenharmony_ci generates falling edge interrupts, however, additional board logic 148c2ecf20Sopenharmony_ci might invert the signal. 158c2ecf20Sopenharmony_ci- pinctrl-names: List of assigned state names, see pinctrl binding documentation. 168c2ecf20Sopenharmony_ci- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line, 178c2ecf20Sopenharmony_ci see also generic and your platform specific pinctrl binding 188c2ecf20Sopenharmony_ci documentation. 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ciOptional properties: 218c2ecf20Sopenharmony_ci- spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60. 228c2ecf20Sopenharmony_ci According to the ENC28J80 datasheet, the chip allows a maximum of 20 MHz, however, 238c2ecf20Sopenharmony_ci board designs may need to limit this value. 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ciThe MAC address will be determined using the optional properties 268c2ecf20Sopenharmony_cidefined in ethernet.txt. 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ciExample (for NXP i.MX28 with pin control stuff for GPIO irq): 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci ssp2: ssp@80014000 { 318c2ecf20Sopenharmony_ci compatible = "fsl,imx28-spi"; 328c2ecf20Sopenharmony_ci pinctrl-names = "default"; 338c2ecf20Sopenharmony_ci pinctrl-0 = <&spi2_pins_b &spi2_sck_cfg>; 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci enc28j60: ethernet@0 { 368c2ecf20Sopenharmony_ci compatible = "microchip,enc28j60"; 378c2ecf20Sopenharmony_ci pinctrl-names = "default"; 388c2ecf20Sopenharmony_ci pinctrl-0 = <&enc28j60_pins>; 398c2ecf20Sopenharmony_ci reg = <0>; 408c2ecf20Sopenharmony_ci interrupt-parent = <&gpio3>; 418c2ecf20Sopenharmony_ci interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 428c2ecf20Sopenharmony_ci spi-max-frequency = <12000000>; 438c2ecf20Sopenharmony_ci }; 448c2ecf20Sopenharmony_ci }; 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci pinctrl@80018000 { 478c2ecf20Sopenharmony_ci enc28j60_pins: enc28j60_pins@0 { 488c2ecf20Sopenharmony_ci reg = <0>; 498c2ecf20Sopenharmony_ci fsl,pinmux-ids = < 508c2ecf20Sopenharmony_ci MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */ 518c2ecf20Sopenharmony_ci >; 528c2ecf20Sopenharmony_ci fsl,drive-strength = <MXS_DRIVE_4mA>; 538c2ecf20Sopenharmony_ci fsl,voltage = <MXS_VOLTAGE_HIGH>; 548c2ecf20Sopenharmony_ci fsl,pull-up = <MXS_PULL_DISABLE>; 558c2ecf20Sopenharmony_ci }; 568c2ecf20Sopenharmony_ci }; 57