18c2ecf20Sopenharmony_ci* Andestech L2 cache Controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe level-2 cache controller plays an important role in reducing memory latency 48c2ecf20Sopenharmony_cifor high performance systems, such as thoese designs with AndesCore processors. 58c2ecf20Sopenharmony_ciLevel-2 cache controller in general enhances overall system performance 68c2ecf20Sopenharmony_cisignigicantly and the system power consumption might be reduced as well by 78c2ecf20Sopenharmony_cireducing DRAM accesses. 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciThis binding specifies what properties must be available in the device tree 108c2ecf20Sopenharmony_cirepresentation of an Andestech L2 cache controller. 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ciRequired properties: 138c2ecf20Sopenharmony_ci - compatible: 148c2ecf20Sopenharmony_ci Usage: required 158c2ecf20Sopenharmony_ci Value type: <string> 168c2ecf20Sopenharmony_ci Definition: "andestech,atl2c" 178c2ecf20Sopenharmony_ci - reg : Physical base address and size of cache controller's memory mapped 188c2ecf20Sopenharmony_ci - cache-unified : Specifies the cache is a unified cache. 198c2ecf20Sopenharmony_ci - cache-level : Should be set to 2 for a level 2 cache. 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci* Example 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci cache-controller@e0500000 { 248c2ecf20Sopenharmony_ci compatible = "andestech,atl2c"; 258c2ecf20Sopenharmony_ci reg = <0xe0500000 0x1000>; 268c2ecf20Sopenharmony_ci cache-unified; 278c2ecf20Sopenharmony_ci cache-level = <2>; 288c2ecf20Sopenharmony_ci }; 29