18c2ecf20Sopenharmony_ciNVIDIA Tegra NAND Flash controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci- compatible: Must be one of: 58c2ecf20Sopenharmony_ci - "nvidia,tegra20-nand" 68c2ecf20Sopenharmony_ci- reg: MMIO address range 78c2ecf20Sopenharmony_ci- interrupts: interrupt output of the NFC controller 88c2ecf20Sopenharmony_ci- clocks: Must contain an entry for each entry in clock-names. 98c2ecf20Sopenharmony_ci See ../clocks/clock-bindings.txt for details. 108c2ecf20Sopenharmony_ci- clock-names: Must include the following entries: 118c2ecf20Sopenharmony_ci - nand 128c2ecf20Sopenharmony_ci- resets: Must contain an entry for each entry in reset-names. 138c2ecf20Sopenharmony_ci See ../reset/reset.txt for details. 148c2ecf20Sopenharmony_ci- reset-names: Must include the following entries: 158c2ecf20Sopenharmony_ci - nand 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciOptional children nodes: 188c2ecf20Sopenharmony_ciIndividual NAND chips are children of the NAND controller node. Currently 198c2ecf20Sopenharmony_cionly one NAND chip supported. 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ciRequired children node properties: 228c2ecf20Sopenharmony_ci- reg: An integer ranging from 1 to 6 representing the CS line to use. 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ciOptional children node properties: 258c2ecf20Sopenharmony_ci- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only 268c2ecf20Sopenharmony_ci "hw" is supported. 278c2ecf20Sopenharmony_ci- nand-ecc-algo: string, algorithm of NAND ECC. 288c2ecf20Sopenharmony_ci Supported values with "hw" ECC mode are: "rs", "bch". 298c2ecf20Sopenharmony_ci- nand-bus-width : See nand-controller.yaml 308c2ecf20Sopenharmony_ci- nand-on-flash-bbt: See nand-controller.yaml 318c2ecf20Sopenharmony_ci- nand-ecc-strength: integer representing the number of bits to correct 328c2ecf20Sopenharmony_ci per ECC step (always 512). Supported strength using HW ECC 338c2ecf20Sopenharmony_ci modes are: 348c2ecf20Sopenharmony_ci - RS: 4, 6, 8 358c2ecf20Sopenharmony_ci - BCH: 4, 8, 14, 16 368c2ecf20Sopenharmony_ci- nand-ecc-maximize: See nand-controller.yaml 378c2ecf20Sopenharmony_ci- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM 388c2ecf20Sopenharmony_ci are chosen. 398c2ecf20Sopenharmony_ci- wp-gpios: GPIO specifier for the write protect pin. 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ciOptional child node of NAND chip nodes: 428c2ecf20Sopenharmony_ciPartitions: see partition.txt 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci Example: 458c2ecf20Sopenharmony_ci nand-controller@70008000 { 468c2ecf20Sopenharmony_ci compatible = "nvidia,tegra20-nand"; 478c2ecf20Sopenharmony_ci reg = <0x70008000 0x100>; 488c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 498c2ecf20Sopenharmony_ci clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; 508c2ecf20Sopenharmony_ci clock-names = "nand"; 518c2ecf20Sopenharmony_ci resets = <&tegra_car 13>; 528c2ecf20Sopenharmony_ci reset-names = "nand"; 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci nand@0 { 558c2ecf20Sopenharmony_ci reg = <0>; 568c2ecf20Sopenharmony_ci #address-cells = <1>; 578c2ecf20Sopenharmony_ci #size-cells = <1>; 588c2ecf20Sopenharmony_ci nand-bus-width = <8>; 598c2ecf20Sopenharmony_ci nand-on-flash-bbt; 608c2ecf20Sopenharmony_ci nand-ecc-algo = "bch"; 618c2ecf20Sopenharmony_ci nand-ecc-strength = <8>; 628c2ecf20Sopenharmony_ci wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; 638c2ecf20Sopenharmony_ci }; 648c2ecf20Sopenharmony_ci }; 65