18c2ecf20Sopenharmony_ciMacronix Raw NAND Controller Device Tree Bindings 28c2ecf20Sopenharmony_ci------------------------------------------------- 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciRequired properties: 58c2ecf20Sopenharmony_ci- compatible: should be "mxic,multi-itfc-v009-nand-controller" 68c2ecf20Sopenharmony_ci- reg: should contain 1 entry for the registers 78c2ecf20Sopenharmony_ci- #address-cells: should be set to 1 88c2ecf20Sopenharmony_ci- #size-cells: should be set to 0 98c2ecf20Sopenharmony_ci- interrupts: interrupt line connected to this raw NAND controller 108c2ecf20Sopenharmony_ci- clock-names: should contain "ps", "send" and "send_dly" 118c2ecf20Sopenharmony_ci- clocks: should contain 3 phandles for the "ps", "send" and 128c2ecf20Sopenharmony_ci "send_dly" clocks 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ciChildren nodes: 158c2ecf20Sopenharmony_ci- children nodes represent the available NAND chips. 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciSee Documentation/devicetree/bindings/mtd/nand-controller.yaml 188c2ecf20Sopenharmony_cifor more details on generic bindings. 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ciExample: 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci nand: nand-controller@43c30000 { 238c2ecf20Sopenharmony_ci compatible = "mxic,multi-itfc-v009-nand-controller"; 248c2ecf20Sopenharmony_ci reg = <0x43c30000 0x10000>; 258c2ecf20Sopenharmony_ci #address-cells = <1>; 268c2ecf20Sopenharmony_ci #size-cells = <0>; 278c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>; 288c2ecf20Sopenharmony_ci clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>; 298c2ecf20Sopenharmony_ci clock-names = "send", "send_dly", "ps"; 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci nand@0 { 328c2ecf20Sopenharmony_ci reg = <0>; 338c2ecf20Sopenharmony_ci nand-ecc-mode = "soft"; 348c2ecf20Sopenharmony_ci nand-ecc-algo = "bch"; 358c2ecf20Sopenharmony_ci }; 368c2ecf20Sopenharmony_ci }; 37