18c2ecf20Sopenharmony_ciCFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciFlash chips (Memory Technology Devices) are often used for solid state 48c2ecf20Sopenharmony_cifile systems on embedded devices. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci - compatible : should contain the specific model of mtd chip(s) 78c2ecf20Sopenharmony_ci used, if known, followed by either "cfi-flash", "jedec-flash", 88c2ecf20Sopenharmony_ci "mtd-ram" or "mtd-rom". 98c2ecf20Sopenharmony_ci - reg : Address range(s) of the mtd chip(s) 108c2ecf20Sopenharmony_ci It's possible to (optionally) define multiple "reg" tuples so that 118c2ecf20Sopenharmony_ci non-identical chips can be described in one node. 128c2ecf20Sopenharmony_ci - bank-width : Width (in bytes) of the bank. Equal to the 138c2ecf20Sopenharmony_ci device width times the number of interleaved chips. 148c2ecf20Sopenharmony_ci - device-width : (optional) Width of a single mtd chip. If 158c2ecf20Sopenharmony_ci omitted, assumed to be equal to 'bank-width'. 168c2ecf20Sopenharmony_ci - #address-cells, #size-cells : Must be present if the device has 178c2ecf20Sopenharmony_ci sub-nodes representing partitions (see below). In this case 188c2ecf20Sopenharmony_ci both #address-cells and #size-cells must be equal to 1. 198c2ecf20Sopenharmony_ci - no-unaligned-direct-access: boolean to disable the default direct 208c2ecf20Sopenharmony_ci mapping of the flash. 218c2ecf20Sopenharmony_ci On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause 228c2ecf20Sopenharmony_ci problems with JFFS2 usage, as the local bus (LPB) doesn't support 238c2ecf20Sopenharmony_ci unaligned accesses as implemented in the JFFS2 code via memcpy(). 248c2ecf20Sopenharmony_ci By defining "no-unaligned-direct-access", the flash will not be 258c2ecf20Sopenharmony_ci exposed directly to the MTD users (e.g. JFFS2) any more. 268c2ecf20Sopenharmony_ci - linux,mtd-name: allow to specify the mtd name for retro capability with 278c2ecf20Sopenharmony_ci physmap-flash drivers as boot loader pass the mtd partition via the old 288c2ecf20Sopenharmony_ci device name physmap-flash. 298c2ecf20Sopenharmony_ci - use-advanced-sector-protection: boolean to enable support for the 308c2ecf20Sopenharmony_ci advanced sector protection (Spansion: PPB - Persistent Protection 318c2ecf20Sopenharmony_ci Bits) locking. 328c2ecf20Sopenharmony_ci - addr-gpios : (optional) List of GPIO descriptors that will be used to 338c2ecf20Sopenharmony_ci address the MSBs address lines. The order goes from LSB to MSB. 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ciFor JEDEC compatible devices, the following additional properties 368c2ecf20Sopenharmony_ciare defined: 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci - vendor-id : Contains the flash chip's vendor id (1 byte). 398c2ecf20Sopenharmony_ci - device-id : Contains the flash chip's device id (1 byte). 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ciFor ROM compatible devices (and ROM fallback from cfi-flash), the following 428c2ecf20Sopenharmony_ciadditional (optional) property is defined: 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci - erase-size : The chip's physical erase block size in bytes. 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci The device tree may optionally contain endianness property. 478c2ecf20Sopenharmony_ci little-endian or big-endian : It Represents the endianness that should be used 488c2ecf20Sopenharmony_ci by the controller to properly read/write data 498c2ecf20Sopenharmony_ci from/to the flash. If this property is missing, 508c2ecf20Sopenharmony_ci the endianness is chosen by the system 518c2ecf20Sopenharmony_ci (potentially based on extra configuration options). 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ciThe device tree may optionally contain sub-nodes describing partitions of the 548c2ecf20Sopenharmony_ciaddress space. See partition.txt for more detail. 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ciExample: 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci flash@ff000000 { 598c2ecf20Sopenharmony_ci compatible = "amd,am29lv128ml", "cfi-flash"; 608c2ecf20Sopenharmony_ci reg = <ff000000 01000000>; 618c2ecf20Sopenharmony_ci bank-width = <4>; 628c2ecf20Sopenharmony_ci device-width = <1>; 638c2ecf20Sopenharmony_ci #address-cells = <1>; 648c2ecf20Sopenharmony_ci #size-cells = <1>; 658c2ecf20Sopenharmony_ci fs@0 { 668c2ecf20Sopenharmony_ci label = "fs"; 678c2ecf20Sopenharmony_ci reg = <0 f80000>; 688c2ecf20Sopenharmony_ci }; 698c2ecf20Sopenharmony_ci firmware@f80000 { 708c2ecf20Sopenharmony_ci label ="firmware"; 718c2ecf20Sopenharmony_ci reg = <f80000 80000>; 728c2ecf20Sopenharmony_ci read-only; 738c2ecf20Sopenharmony_ci }; 748c2ecf20Sopenharmony_ci }; 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ciHere an example with multiple "reg" tuples: 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ci flash@f0000000,0 { 798c2ecf20Sopenharmony_ci #address-cells = <1>; 808c2ecf20Sopenharmony_ci #size-cells = <1>; 818c2ecf20Sopenharmony_ci compatible = "intel,PC48F4400P0VB", "cfi-flash"; 828c2ecf20Sopenharmony_ci reg = <0 0x00000000 0x02000000 838c2ecf20Sopenharmony_ci 0 0x02000000 0x02000000>; 848c2ecf20Sopenharmony_ci bank-width = <2>; 858c2ecf20Sopenharmony_ci partition@0 { 868c2ecf20Sopenharmony_ci label = "test-part1"; 878c2ecf20Sopenharmony_ci reg = <0 0x04000000>; 888c2ecf20Sopenharmony_ci }; 898c2ecf20Sopenharmony_ci }; 908c2ecf20Sopenharmony_ci 918c2ecf20Sopenharmony_ciAn example using SRAM: 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_ci sram@2,0 { 948c2ecf20Sopenharmony_ci compatible = "samsung,k6f1616u6a", "mtd-ram"; 958c2ecf20Sopenharmony_ci reg = <2 0 0x00200000>; 968c2ecf20Sopenharmony_ci bank-width = <2>; 978c2ecf20Sopenharmony_ci }; 988c2ecf20Sopenharmony_ci 998c2ecf20Sopenharmony_ciAn example using gpio-addrs 1008c2ecf20Sopenharmony_ci 1018c2ecf20Sopenharmony_ci flash@20000000 { 1028c2ecf20Sopenharmony_ci #address-cells = <1>; 1038c2ecf20Sopenharmony_ci #size-cells = <1>; 1048c2ecf20Sopenharmony_ci compatible = "cfi-flash", "jedec-flash"; 1058c2ecf20Sopenharmony_ci reg = <0x20000000 0x02000000>; 1068c2ecf20Sopenharmony_ci ranges = <0 0x00000000 0x02000000 1078c2ecf20Sopenharmony_ci 1 0x02000000 0x02000000>; 1088c2ecf20Sopenharmony_ci bank-width = <2>; 1098c2ecf20Sopenharmony_ci addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 1108c2ecf20Sopenharmony_ci partition@0 { 1118c2ecf20Sopenharmony_ci label = "test-part1"; 1128c2ecf20Sopenharmony_ci reg = <0 0x04000000>; 1138c2ecf20Sopenharmony_ci }; 1148c2ecf20Sopenharmony_ci }; 115