18c2ecf20Sopenharmony_ciFreescale Localbus UPM programmed to work with NAND flash
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible : "fsl,upm-nand".
58c2ecf20Sopenharmony_ci- reg : should specify localbus chip select and size used for the chip.
68c2ecf20Sopenharmony_ci- fsl,upm-addr-offset : UPM pattern offset for the address latch.
78c2ecf20Sopenharmony_ci- fsl,upm-cmd-offset : UPM pattern offset for the command latch.
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ciOptional properties:
108c2ecf20Sopenharmony_ci- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
118c2ecf20Sopenharmony_ci	The corresponding address lines are used to select the chip.
128c2ecf20Sopenharmony_ci- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
138c2ecf20Sopenharmony_ci	(R/B#). For multi-chip devices, "n" GPIO definitions are required
148c2ecf20Sopenharmony_ci	according to the number of chips.
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ciDeprecated properties:
178c2ecf20Sopenharmony_ci- fsl,upm-wait-flags : add chip-dependent short delays after running the
188c2ecf20Sopenharmony_ci	UPM pattern (0x1), after writing a data byte (0x2) or after
198c2ecf20Sopenharmony_ci	writing out a buffer (0x4).
208c2ecf20Sopenharmony_ci- chip-delay : chip dependent delay for transferring data from array to
218c2ecf20Sopenharmony_ci	read registers (tR). Required if property "gpios" is not used
228c2ecf20Sopenharmony_ci	(R/B# pins not connected).
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ciEach flash chip described may optionally contain additional sub-nodes
258c2ecf20Sopenharmony_cidescribing partitions of the address space. See partition.txt for more
268c2ecf20Sopenharmony_cidetail.
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ciExamples:
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ciupm@1,0 {
318c2ecf20Sopenharmony_ci	compatible = "fsl,upm-nand";
328c2ecf20Sopenharmony_ci	reg = <1 0 1>;
338c2ecf20Sopenharmony_ci	fsl,upm-addr-offset = <16>;
348c2ecf20Sopenharmony_ci	fsl,upm-cmd-offset = <8>;
358c2ecf20Sopenharmony_ci	gpios = <&qe_pio_e 18 0>;
368c2ecf20Sopenharmony_ci
378c2ecf20Sopenharmony_ci	flash {
388c2ecf20Sopenharmony_ci		#address-cells = <1>;
398c2ecf20Sopenharmony_ci		#size-cells = <1>;
408c2ecf20Sopenharmony_ci		compatible = "...";
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ci		partition@0 {
438c2ecf20Sopenharmony_ci			...
448c2ecf20Sopenharmony_ci		};
458c2ecf20Sopenharmony_ci	};
468c2ecf20Sopenharmony_ci};
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ciupm@3,0 {
498c2ecf20Sopenharmony_ci	#address-cells = <0>;
508c2ecf20Sopenharmony_ci	#size-cells = <0>;
518c2ecf20Sopenharmony_ci	compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
528c2ecf20Sopenharmony_ci	reg = <3 0x0 0x800>;
538c2ecf20Sopenharmony_ci	fsl,upm-addr-offset = <0x10>;
548c2ecf20Sopenharmony_ci	fsl,upm-cmd-offset = <0x08>;
558c2ecf20Sopenharmony_ci	/* Multi-chip NAND device */
568c2ecf20Sopenharmony_ci	fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ci	nand@0 {
598c2ecf20Sopenharmony_ci		#address-cells = <1>;
608c2ecf20Sopenharmony_ci		#size-cells = <1>;
618c2ecf20Sopenharmony_ci
628c2ecf20Sopenharmony_ci		partition@0 {
638c2ecf20Sopenharmony_ci			    label = "fs";
648c2ecf20Sopenharmony_ci			    reg = <0x00000000 0x10000000>;
658c2ecf20Sopenharmony_ci		};
668c2ecf20Sopenharmony_ci	};
678c2ecf20Sopenharmony_ci};
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