18c2ecf20Sopenharmony_ciAmlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis file documents the properties in addition to those available in 48c2ecf20Sopenharmony_cithe MTD NAND bindings. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired properties: 78c2ecf20Sopenharmony_ci- compatible : contains one of: 88c2ecf20Sopenharmony_ci - "amlogic,meson-gxl-nfc" 98c2ecf20Sopenharmony_ci - "amlogic,meson-axg-nfc" 108c2ecf20Sopenharmony_ci- clocks : 118c2ecf20Sopenharmony_ci A list of phandle + clock-specifier pairs for the clocks listed 128c2ecf20Sopenharmony_ci in clock-names. 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci- clock-names: Should contain the following: 158c2ecf20Sopenharmony_ci "core" - NFC module gate clock 168c2ecf20Sopenharmony_ci "device" - device clock from eMMC sub clock controller 178c2ecf20Sopenharmony_ci "rx" - rx clock phase 188c2ecf20Sopenharmony_ci "tx" - tx clock phase 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC 218c2ecf20Sopenharmony_ci controller port C 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ciOptional children nodes: 248c2ecf20Sopenharmony_ciChildren nodes represent the available nand chips. 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ciOther properties: 278c2ecf20Sopenharmony_cisee Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings. 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ciExample demonstrate on AXG SoC: 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci sd_emmc_c_clkc: mmc@7000 { 328c2ecf20Sopenharmony_ci compatible = "amlogic,meson-axg-mmc-clkc", "syscon"; 338c2ecf20Sopenharmony_ci reg = <0x0 0x7000 0x0 0x800>; 348c2ecf20Sopenharmony_ci }; 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_ci nand-controller@7800 { 378c2ecf20Sopenharmony_ci compatible = "amlogic,meson-axg-nfc"; 388c2ecf20Sopenharmony_ci reg = <0x0 0x7800 0x0 0x100>; 398c2ecf20Sopenharmony_ci #address-cells = <1>; 408c2ecf20Sopenharmony_ci #size-cells = <0>; 418c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci clocks = <&clkc CLKID_SD_EMMC_C>, 448c2ecf20Sopenharmony_ci <&sd_emmc_c_clkc CLKID_MMC_DIV>, 458c2ecf20Sopenharmony_ci <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, 468c2ecf20Sopenharmony_ci <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; 478c2ecf20Sopenharmony_ci clock-names = "core", "device", "rx", "tx"; 488c2ecf20Sopenharmony_ci amlogic,mmc-syscon = <&sd_emmc_c_clkc>; 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci pinctrl-names = "default"; 518c2ecf20Sopenharmony_ci pinctrl-0 = <&nand_pins>; 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ci nand@0 { 548c2ecf20Sopenharmony_ci reg = <0>; 558c2ecf20Sopenharmony_ci #address-cells = <1>; 568c2ecf20Sopenharmony_ci #size-cells = <1>; 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci nand-on-flash-bbt; 598c2ecf20Sopenharmony_ci }; 608c2ecf20Sopenharmony_ci }; 61