18c2ecf20Sopenharmony_ci* ARM PrimeCell MultiMedia Card Interface (MMCI) PL180/1
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThe ARM PrimeCell MMCI PL180 and PL181 provides an interface for
48c2ecf20Sopenharmony_cireading and writing to MultiMedia and SD cards alike.
58c2ecf20Sopenharmony_ci
68c2ecf20Sopenharmony_ciThis file documents differences between the core properties described
78c2ecf20Sopenharmony_ciby mmc.txt and the properties used by the mmci driver. Using "st" as
88c2ecf20Sopenharmony_cithe prefix for a property, indicates support by the ST Micro variant.
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ciRequired properties:
118c2ecf20Sopenharmony_ci- compatible             : contains "arm,pl18x", "arm,primecell".
128c2ecf20Sopenharmony_ci- vmmc-supply            : phandle to the regulator device tree node, mentioned
138c2ecf20Sopenharmony_ci                           as the VCC/VDD supply in the eMMC/SD specs.
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ciOptional properties:
168c2ecf20Sopenharmony_ci- arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides
178c2ecf20Sopenharmony_ci                           the ID provided by the HW
188c2ecf20Sopenharmony_ci- resets                 : phandle to internal reset line.
198c2ecf20Sopenharmony_ci			   Should be defined for sdmmc variant.
208c2ecf20Sopenharmony_ci- vqmmc-supply           : phandle to the regulator device tree node, mentioned
218c2ecf20Sopenharmony_ci                           as the VCCQ/VDD_IO supply in the eMMC/SD specs.
228c2ecf20Sopenharmony_cispecific for ux500 variant:
238c2ecf20Sopenharmony_ci- st,sig-dir-dat0        : bus signal direction pin used for DAT[0].
248c2ecf20Sopenharmony_ci- st,sig-dir-dat2        : bus signal direction pin used for DAT[2].
258c2ecf20Sopenharmony_ci- st,sig-dir-dat31       : bus signal direction pin used for DAT[3] and DAT[1].
268c2ecf20Sopenharmony_ci- st,sig-dir-dat74       : bus signal direction pin used for DAT[4] to DAT[7].
278c2ecf20Sopenharmony_ci- st,sig-dir-cmd         : cmd signal direction pin used for CMD.
288c2ecf20Sopenharmony_ci- st,sig-pin-fbclk       : feedback clock signal pin used.
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_cispecific for sdmmc variant:
318c2ecf20Sopenharmony_ci- reg			 : a second base register may be defined if a delay
328c2ecf20Sopenharmony_ci                           block is present and used for tuning.
338c2ecf20Sopenharmony_ci- st,sig-dir             : signal direction polarity used for cmd, dat0 dat123.
348c2ecf20Sopenharmony_ci- st,neg-edge            : data & command phase relation, generated on
358c2ecf20Sopenharmony_ci                           sd clock falling edge.
368c2ecf20Sopenharmony_ci- st,use-ckin            : use ckin pin from an external driver to sample
378c2ecf20Sopenharmony_ci                           the receive data (example: with voltage
388c2ecf20Sopenharmony_ci			   switch transceiver).
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ciDeprecated properties:
418c2ecf20Sopenharmony_ci- mmc-cap-mmc-highspeed  : indicates whether MMC is high speed capable.
428c2ecf20Sopenharmony_ci- mmc-cap-sd-highspeed   : indicates whether SD is high speed capable.
438c2ecf20Sopenharmony_ci
448c2ecf20Sopenharmony_ciExample:
458c2ecf20Sopenharmony_ci
468c2ecf20Sopenharmony_cisdi0_per1@80126000 {
478c2ecf20Sopenharmony_ci	compatible = "arm,pl18x", "arm,primecell";
488c2ecf20Sopenharmony_ci	reg = <0x80126000 0x1000>;
498c2ecf20Sopenharmony_ci	interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
508c2ecf20Sopenharmony_ci
518c2ecf20Sopenharmony_ci	dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
528c2ecf20Sopenharmony_ci	       <&dma 29 0 0x0>; /* Logical - MemToDev */
538c2ecf20Sopenharmony_ci	dma-names = "rx", "tx";
548c2ecf20Sopenharmony_ci
558c2ecf20Sopenharmony_ci	clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
568c2ecf20Sopenharmony_ci	clock-names = "sdi", "apb_pclk";
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ci	max-frequency = <100000000>;
598c2ecf20Sopenharmony_ci	bus-width = <4>;
608c2ecf20Sopenharmony_ci	cap-sd-highspeed;
618c2ecf20Sopenharmony_ci	cap-mmc-highspeed;
628c2ecf20Sopenharmony_ci	cd-gpios  = <&gpio2 31 0x4>; // 95
638c2ecf20Sopenharmony_ci	st,sig-dir-dat0;
648c2ecf20Sopenharmony_ci	st,sig-dir-dat2;
658c2ecf20Sopenharmony_ci	st,sig-dir-cmd;
668c2ecf20Sopenharmony_ci	st,sig-pin-fbclk;
678c2ecf20Sopenharmony_ci
688c2ecf20Sopenharmony_ci	vmmc-supply = <&ab8500_ldo_aux3_reg>;
698c2ecf20Sopenharmony_ci	vqmmc-supply = <&vmmci>;
708c2ecf20Sopenharmony_ci
718c2ecf20Sopenharmony_ci	pinctrl-names = "default", "sleep";
728c2ecf20Sopenharmony_ci	pinctrl-0 = <&sdi0_default_mode>;
738c2ecf20Sopenharmony_ci	pinctrl-1 = <&sdi0_sleep_mode>;
748c2ecf20Sopenharmony_ci};
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